UPSD33XX Datasheet, PDF (56/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Figure 17. MCU I/O Cell Block Diagram for Port 1
Select_Alternate_Func
Digital_Alt_Func_Data_Out
P1.X SFR Read Latch
(for R-M-W instructions)
MCU_Reset
8032 Data Bus Bit
GPIO P1.X SFR
Write Latch
DELAY,
1 MCU_CLK
PRE
D
Q
SFR
P1.X
Latch _Q
IN 1 ^SEL
MUX Y
IN 0
DELAY,
1 MCU_CLK
P1.X SFR Read Pin
Analog_Alt_Func_En
Digital_Pin_Data_In
Analog_Pin_In
Figure 18. MCU I/O Cell Block Diagram for Port 3
Enable_I2C
Select_Alternate_Func
Digital_Alt_Func_Data_Out
P3.X SFR Read Latch
(for R-M-W instructions)
MCU_Reset
8032 Data Bus Bit
GPIO P3.X SFR
Write Latch
Disables High-Side Driver
DELAY,
1 MCU_CLK
PRE
D _SFR Q
P3.X
Latch _Q
IN 1 ^SEL
MUX Y
IN 0
DELAY,
1 MCU_CLK
P3.X SFR Read Pin
Digital_Pin_Data_In
VCC
VCC
WEAK
PULL-UP, B
HIGH
SIDE
VCC
STONGER
PULL-UP, A
P1.X Pin
LOW
SIDE
AI09600
VCC
VCC
WEAK
PULL-UP, B
HIGH
SIDE
VCC
STONGER
PULL-UP, A
P3.X Pin
LOW
SIDE
AI09601
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