UPSD33XX Datasheet, PDF (32/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
uPSD33xx INSTRUCTION SET SUMMARY
Tables 6 through 11 list all of the instructions sup-
ported by the uPSD33xx, including the number of
bytes and number of machine cycles required to
implement each instruction. This is the standard
8051 instruction set.
The meaning of “machine cycles” is how many
8032 MCU core machine cycles are required to
execute the instruction. The “native” duration of all
machine cycles is set by the memory wait state
settings in the SFR, BUSCON, and the MCU clock
divider selections in the SFR, CCON0 (i.e. a ma-
chine cycle is typically set to 4 MCU clocks for a 5V
uPSD33xx). However, an individual machine cycle
may grow in duration when either of two things
happen:
1. a stall is imposed while loading the 8032 Pre-
Fetch Queue (PFQ); or
2. the occurrence of a cache miss in the Branch
Cache (BC) during a branch in program
execution flow.
See 8032 MCU CORE PERFORMANCE
ENHANCEMENTS, page 17 or more details.
But generally speaking, during typical program ex-
ecution, the PFQ is not empty and the BC has no
misses, producing very good performance without
extending the duration of any machine cycles.
The uPSD33xx Programmers Guide describes
each instruction operation in detail.
Table 6. Arithmetic Instruction Set
Mnemonic⁽¹⁾
and Use
Description
ADD
A, Rn
Add register to ACC
ADD
A, Direct
Add direct byte to ACC
ADD
A, @Ri
Add indirect SRAM to ACC
ADD
A, #data
Add immediate data to ACC
ADDC
A, Rn
Add register to ACC with carry
ADDC
A, direct
Add direct byte to ACC with carry
ADDC
A, @Ri
Add indirect SRAM to ACC with carry
ADDC
A, #data
Add immediate data to ACC with carry
SUBB
A, Rn
Subtract register from ACC with borrow
SUBB
A, direct
Subtract direct byte from ACC with borrow
SUBB
A, @Ri
Subtract indirect SRAM from ACC with borrow
SUBB
A, #data
Subtract immediate data from ACC with borrow
INC
A
Increment A
INC
Rn
Increment register
INC
direct
Increment direct byte
INC
@Ri
Increment indirect SRAM
DEC
A
Decrement ACC
DEC
Rn
Decrement register
DEC
direct
Decrement direct byte
DEC
@Ri
Decrement indirect SRAM
INC
DPTR
Increment Data Pointer
MUL
AB
Multiply ACC and B
DIV
AB
Divide ACC by B
DA
A
Decimal adjust ACC
Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.
Length/Cycles
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
1 byte/2 cycle
1 byte/4 cycle
1 byte/4 cycle
1 byte/1 cycle
32/231