UPSD33XX Datasheet, PDF (105/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
I²C START Sample Setting (S1SETUP)
The S1SETUP register (Table 55) determines how
many times an I²C bus START condition will be
sampled before the SIOE validates the START
condition, giving the SIOE the ability to reject noise
or illegal transmissions.
Because the minimum duration of an START con-
dition varies with I²C bus speed (f_SCL), and also
because the uPSD33xx may be operated with a
wide variety of frequencies (f_OSC), it is necessary
to scale the number of samples per START condi-
tion based on f_OSC and f_SCL.
In Slave mode, the SIOE recognizes the beginning
of a START condition when it detects a '1'-to-'0'
transition on the SDA bus line while the SCL line is
high (see Figure 39., page 97). The SIOE must
then validate the START condition by sampling the
bus lines to ensure SDA remains low and SCL re-
mains high for a minimum amount of hold time,
t_HLDSTA. Once validated, the SIOE begins receiv-
ing the address byte that follows the START con-
dition.
If the EN_SS Bit (in the S1SETUP Register) is not
set, then the SIOE will sample only once after de-
tecting the '1'-to-'0' transition on SDA. This single
sample is taken 1/f_OSC seconds after the initial 1-
to-0 transition was detected. However, more sam-
ples should be taken to ensure there is a valid
START condition.
To take more samples, the SIOE should be initial-
ized such that the EN_SS Bit is set, and a value is
written to the SMPL_SET[6:0] field of the
S1SETUP Register to specify how many samples
to take. The goal is to take a good number of sam-
ples during the minimum START condition hold
time, t_HLDSTA, but no so many samples that the
bus will be sampled after t_HLDSTA expires.
Table 56., page 106 describes the relationship be-
tween the contents of S1SETUP and the resulting
number of I²C bus samples that SIOE will take af-
ter detecting the 1-to-0 transition on SDA of a
START condition.
Important: Keep in mind that the time between
samples is always 1/f_OSC.
The minimum START
TA^{, is different for the}
condition hold time,
three common I²C
t_HLDS-
speed
categories per Table 57., page 106.
Table 55. S1SETUP: I²C START Condition Sample Setup register (SFR DBh, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EN_SS
SMPL_SET[6:0]
Details
Bit
Symbol
R/W
Function
Enable Sample Setup
7
EN_SS
R/W
EN_SS = 1 will force the SIOE to sample⁽¹⁾ a START condition on the bus
the number of times specified in SMPL_SET[6:0].
EN_SS = 0 means the SIOE will sample⁽¹⁾ a START condition only one
time, regardless of the contents of SMPL_SET[6:0].
6:0
SMPL_SET
[6:0]
Sample Setting
–
Specifies the number of bus samples⁽¹⁾ taken during a START condition.
See Table 56 for values.
Note: 1. Sampling SCL and SDA lines begins after '1'-to-'0' transition on SDA occurred while SCL is high. Time between samples is 1/f_OSC.
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