UPSD33XX Datasheet, PDF (167/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

Figure 68. Detail of a Single IMC
TO PLD INPUT BUS
FROM AND-OR ARRAY
8032 READ OF PARTICULAR CSIOP IMC REGISTER
8032 DATA BIT
ALE
PIN INPUT
M
U ^{LATCHED INPUT} _{Q D}
X _{GATED INPUT}
(.LD)
PSDsoft
PSDsoft
ALE
M
U
PT CLOCK OR GATE (.LD OR .LE) X
QD
(.LE)
G
uPSD33xx
FROM I/O PORT
LOGIC
INPUT SIGNAL
FROM PIN ON
PORT A, B, or C
INPUT MACROCELL (IMC)
THIS SIGAL IS GANGED TO 3 OTHER
IMCs, GROUPING IMC 0 - 3 or IMC 4 - 7.
AI06603A
Table 90. Input Macrocell Port A⁽¹⁾ (address = csiop + offset 0Ah)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
IMC PA7
IMC PA6
IMC PA5
IMC PA4
IMC PA3
IMC PA2
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’
Table 91. Input Macrocell Port B (address = csiop + offset 0Bh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
IMC PB7
IMC PB6
IMC PB5
IMC PB4
Note: 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’
IMC PB3
IMC PB2
Table 92. Input Macrocell Port C (address = csiop + offset 18h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
IMC PC7
X
X
IMC PC4
IMC PC3
IMC PC2
Note: 1. X = Not guaranteed value, can be read either '1' or '0.' These are JTAG pins.
2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’
Bit 1
IMC PA1
Bit 1
IMC PB1
Bit 1
X
Bit 0
IMC PA0
Bit 0
IMC PB0
Bit 0
X
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