UPSD33XX Datasheet, PDF (186/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Figure 77. Port D Structure
FROM AND-
OR ARRAY
FROM PLD
INPUT BUS
PT OUTPUT ENABLE (.OE)
PSD MODULE RESET
Q ^DIRECTION
CSIOP
REGIS-
8032
DATA
TERS
Q
DRIVE
BITS _D
8032
WR
(MCUI/O)
Q ^{DATA OUT}
CLR
RESET
8032
DATA
BIT
P ^{1 DIRECTION}
D ₂ ^{DRIVE SELECT}
B DATA OUT
M
U
3
4
(MCUI/O)
ENABLE OUT
X ₅ DATA IN (MCUI/O)
8032 RD
ONE of 5
CSIOP
REGISTERS
I/O PORT D
LOGIC
PSDsoft
DRIVE TYPE SELECT
1 = FAST
SLEW RATE
1^O
OUTPUT
U
ENABLE
T
P
PIN
U
OUTPUT
2T
OUTPUT
M
ENABLE
U
X
V_DD V_DD
TYPICAL
PIN, PORT D
CMOS
BUFFER _{PIN INPUT}
NO
HYSTERESIS
FROM DPLD
FROM DPLD EXTERNAL CHIP (ECSx)
TO POWER MANAGEMENT AND PLD INPUT BUS
TO POWER MANAGEMENT
DIRECTLY TO PLD INPUT BUS, NO IMC
CLKIN⁽¹⁾
CSI⁽¹⁾
PD1. PIN, PD2.PIN
Note: 1. Optional function on a specific Port D pin.
AI09182
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