UPSD33XX Datasheet, PDF (181/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Individual Port Structures. Ports A, B, C, and D
have some differences. The structure of each indi-
vidual port is described in the next sections.
Port A Structure. Port A supports the following
operating modes:
■ MCU I/O Mode
■ GPLD Output Mode from Output Macrocells
MCELLABx
■ GPLD Input Mode to Input Macrocells IMCAx
■ Latched Address Output Mode
■ Peripheral I/O Mode
Port A also supports Open Drain/Slew Rate output
drive type options using csiop Drive Select regis-
ters. Pins PA0-PA3 can be configured to fast slew
rate, pins PA4-PA7 can be configured to Open
Drain Mode.
See Figure 74 for details.
Figure 74. Port A Structure
FROM AND-
OR ARRAY
FROM PLD
INPUT BUS
FROM OMC
ALLOCATOR
PT OUTPUT ENABLE (.OE)
WR RD PIO EN PSELx
I/O PORT A
LOGIC
PSD MODULE RESET
Q ^DIRECTION
CSIOP
REGIS-
8032 ^TERS
DATA
Q
DRIVE
BITS _D
8032
WR
Q ^CONTROL
(MCUI/O)
DATA OUT
Q
CLR _RESET
LATCHED ADDR BIT
D BIT, PERIPH I/O MODE
8032
DATA
BIT
1 ^DIRECTION
P ₂ ^{DRIVE SELECT}
D
B
3
CONTROL
DATA OUT
M ₄ ^(MCUI/O)
U ₅ ^{ENABLE OUT}
X ₆ DATA IN (MCUI/O)
PSDsoft
OUTPUT
SELECT
1^O
U
T
P
U
2T
3
M
4_U
X
PERIPHERAL I/O
MODE SETS
DIRECTION
DRIVE TYPE SELECT⁽¹⁾
OE
MUX
1 = OPEN
DRAIN,
PA4 - PA7
1 = FAST
SLEW RATE,
PA0 - PA3
V_DD V_DD
OUTPUT
ENABLE
PIN
OUTPUT
PERIPH I/O
DATA BIT
CMOS
BUFFER _{PIN INPUT}
TYPICAL
PIN, PORT A
8032 RD
ONE of 6
CSIOP
REGISTERS
NO
HYSTERESIS
FROM OMC OUTPUT (MCELLABx)
TO IMCs
IMCA0 - IMCA7
AI09179
Note: 1. Port pins PA0-PA3 are capable of Fast Slew Rate output drive option. Port pins PA4-PA7 are capable of Open Drain output option.
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