UPSD33XX Datasheet, PDF (201/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Debugging the 8032 MCU Module. The 8032
on the MCU module may be debugged in-circuit
using the same four basic JTAG signals as used
for JTAG ISP (TDI, TDO, TCK, TMS). The signals
TSTAT and TERR are not needed for debugging,
and they will not create a problem if they exist on
the circuit board while debugging. The same con-
nector specified in Figure 83., page 199 can be
used for ISP or for 8032 debugging. There are 3rd
party suppliers of uPSD33xx JTAG debugging
equipment (check www.st.com/psm). These are
small pods which connect to a PC (or notebook
computer) using a USB interface, and they are
driven by an 8032 Integrated Development Envi-
ronment (IDE) running on the PC.
Standard debugging features are provided
through this JTAG interface such as single-step,
breakpoints, trace, memory dump and fill, and oth-
ers. There is also a dedicated Debug pin (shown
in Figure 80., page 195) which can be configured
as an output to trigger external devices upon a
programmable internal event (e.g., breakpoint
match), or the pin can be configured as an input so
an external device can initiate an internal debug
event (e.g., break execution). The Debug pin func-
tion is configured by the 8032 IDE debug software
tool. See DEBUG UNIT, page 39 for more details.
The Debug signal should always be pulled up ex-
ternally with a weak pull-up (100K minimum) to
V_CC even if nothing is connected to it, as shown in
Figure 81., page 196 and Figure 82., page 198.
JTAG Security Setting. A programmable securi-
ty bit in the PSD Module protects its contents from
unauthorized viewing and copying. The security
bit is set by clicking on the “Additional PSD Set-
tings” box in the main flow diagram of PSDsoft Ex-
press, then choosing to set the security bit. Once
a file with this setting is programmed into a
uPSD33xx using JTAG ISP, any further attempts
to communicate with the uPSD33xx using JTAG
will be limited. Once secured, the only JTAG oper-
ation allowed is a full-chip erase. No reading or
modifying Flash memory or PLD logic is allowed.
Debugging operations to the MCU Module are
also not allowed. The only way to defeat the secu-
rity bit is to perform a JTAG ISP full-chip erase op-
eration, after which the device is blank and may be
used again. The 8032 on the MCU Module will al-
ways have access to PSM Module memory con-
tents through the 8-bit 8032 data bus connecting
the two die, even while the security bit is set.
Initial Delivery State. When delivered from ST-
Microelectronics, uPSD33xx devices are erased,
meaning all Flash memory and PLD configuration
bits are logic '1.' Firmware and PLD logic configu-
ration must be programmed at least the first time
using JTAG ISP. Subsequent programming of
Flash memory may be performed using JTAG ISP,
JTAG debugging, or the 8032 may run firmware to
program Flash memory (IAP).
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