UPSD33XX Datasheet, PDF (121/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 63. ACON Register (SFR 97h, Reset Value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
AINTF
AINTEN
ADEN
ADS2
ADS1
ADS0
Details
Bit
Symbol
Function
ADC Interrupt flag. This bit must be cleared with software.
Bit 1
ADST
Bit 0
ADSF
7
AINTF 0 = No interrupt request
1 = The AINTF flag is set when ADSF goes from '0' to '1.' Interrupts CPU when both
AINTF and AINTEN are set to '1.'
ADC Interrupt Enable
6
AINTEN _{0 = ADC interrupt is disabled}
1 = ADC interrupt is enabled
ADC Enable Bit
5
ADEN 0 = ADC shut off and consumes no operating current
1 = Enable ADC. After ADC is enabled, 16ms of calibration is needed before ADST Bit is
set.
Analog channel Select
000 Select channel 0 (P1.0)
001 Select channel 0 (P1.1)
4.. 2
ADS2.. 0 010 Select channel 0 (P1.2)
011 Select channel 0 (P1.3)
101 Select channel 0 (P1.5)
110 Select channel 0 (P1.6)
111 Select channel 0 (P1.7)
ADC Start Bit
1
ADST
0 = Force to zero
1 = Start ADC, then after one cycle, the bit is cleared to '0.'
ADC Status Bit
0
ADSF
0 = ADC conversion is not completed
1 = ADC conversion is completed. The bit can also be cleared with software.
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