UPSD33XX Datasheet, PDF (135/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 75. uPSD33xx Memory Configuration
Main Flash Memory
Secondary Flash Memory
Device
Total
Individual
Number of
Total
Individual
Number of
Flash Size Sector Size Sectors (Sector Flash Size Sector Size Sectors (Sector
(bytes)
(bytes)
Select Signal) (bytes)
(bytes)
Select Signal)
uPSD3312 64K
16K
4 (FS0-3)
16K
8K
2 (CSBOOT0-1)
uPSD3333 128K
16K
8 (FS0-7)
32K
8K
4 (CSBOOT0-3)
uPSD3334 256K
32K
8 (FS0-7)
32K
8K
4 (CSBOOT0-3)
uPSD3354 256K
32K
8 (FS0-7)
32K
8K
4 (CSBOOT0-3)
SRAM
SRAM
Size
(bytes)
2K
8K
8K
32K
Runtime Control Registers, CSIOP. A block of
256 bytes is decoded inside the PSD Module for
module control and status (see Table
79., page 145). The base address of these 256 lo-
cations is referred to in this data sheet as csiop
(Chip Select I/O Port), and is selected by the De-
code PLD output signal, CSIOP. The csiop regis-
ters are always viewed by the 8032 as XDATA,
and are accessed with RD and WR signals. The
address range of CSIOP is specified using PSD-
soft Express where the user only has to specify an
address range of 256 bytes, and then the RD or
WR signals are automatically activated for the
specified range. Individual registers within this
block are accessed with an offset from the speci-
fied csiop base address. 39 registers are used out
of the 256 locations to control the output state of I/
O pins, to read I/O pins, to set the memory page,
to control 8032 program and data address space,
to control power management, to READ/WRITE
macrocells inside the General PLD, and other
functions during runtime. Unused locations within
csiop are reserved and should not be accessed.
Memory Page Register. 8032 MCU architecture
has an inherent size limit of 64K bytes in either
program address space or XDATA space. Some
uPSD33xx devices have much more memory that
64K, so special logic such as this page register is
needed to access the extra memory. This 8-bit
page register (Figure 52) can be loaded and read
by the 8032 at runtime as one of the csiop regis-
ters. Page register outputs feed directly into both
PLDs creating extended address signals used to
“page” memory beyond the 64K byte limit (pro-
gram space or XDATA). Most 8051 compilers di-
rectly support memory paging, also known as
memory banking. If memory paging is not needed,
or if not all eight page register bits are needed for
memory paging, the remaining bits may be used in
the General PLD for general logic. Page Register
outputs are cleared to logic ’0’ at reset and power-
up.
Programmable Logic (PLDs) . The uPSD33xx
contains two PLDs (Figure 63., page 157) that
may optionally run in Turbo or Non-Turbo mode.
PLDs operate faster (less propagation delay)
while in Turbo mode but consume more power
than in Non-Turbo mode. Non-Turbo mode allows
the PLDs to go to standby automatically when no
PLD inputs are changing to conserve power.
The logic configuration (from equations) of both
PLDs is stored with non-volatile Flash technology
and the logic is active upon power-up. PLDs may
NOT be programmed by the 8032, PLD program-
ming only occurs through the JTAG interface.
Figure 52. Memory Page Register
Page
Register
8032
Data
Bus
Load or
Read via
csiop +
offset E0h
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
RST
PGR0-7
DPLD
and
GPLD
Chip-
Selects
and
General
Logic
RST
(PSD Module Reset)
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