UPSD33XX Datasheet, PDF (120/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
ANALOG-TO-DIGITAL CONVERTOR (ADC)
The ADC unit in the uPSD33xx is a SAR type ADC
with an SAR register, an auto-zero comparator
and three internal DACs. The unit has 8 input
channels with 10-bit resolution. The A/D converter
has its own V_REF input (80-pin package only),
which specifies the voltage reference for the A/D
operations. The analog to digital converter (A/D)
allows conversion of an analog input to a corre-
sponding 10-bit digital value. The A/D module has
eight analog inputs (P1.0 through P1.7) to an 8x1
multiplexor. One ADC channel is selected by the
bits in the configuration register. The converter
generates a 10-bits result via successive approxi-
mation. The analog supply voltage is connected to
the V_REF input, which powers the resistance lad-
der in the A/D module.
The A/D module has 3 registers, the control regis-
ter ACON, the A/D result register ADAT0, and the
second A/D result register ADAT1. The ADAT0
Register stores Bits 0.. 7 of the converter output,
Bits 8.. 9 are stored in Bits 0..1 of the ADAT1 Reg-
ister. The ACON Register controls the operation of
the A/D converter module. Three of the bits in the
ACON Register select the analog channel inputs,
and the remaining bits control the converter oper-
ation.
ADC channel pin input is enabled by setting the
corresponding bit in the P1SFS0 and P1SFS1
Registers to '1' and the channel select bits in the
ACON Register.
The ADC reference clock (ADCCLK) is generated
from f_OSC divided by the divider in the ADCPS
Register. The ADC operates within a range of 2 to
16MHz, with typical ADCCLK frequency at 8MHz.
The conversion time is 4µs typical at 8MHz.
The processing of conversion starts when the
Start Bit ADST is set to '1.' After one cycle, it is
cleared by hardware. The ADC is monotonic with
no missing codes. Measurement is by continuous
conversion of the analog input. The ADAT Regis-
ter contains the results of the A/D conversion.
When conversion is complete, the result is loaded
into the ADAT. The A/D Conversion Status Bit
ADSF is set to '1.' The block diagram of the A/D
module is shown in Figure 46. The A/D status bit
ADSF is set automatically when A/D conversion is
completed and cleared when A/D conversion is in
process.
In addition, the ADC unit sets the interrupt flag in
the ACON Register after a conversion is complete
(if AINTEN is set to '1'). The ADC interrupts the
CPU when the enable bit AINTEN is set.
Port 1 ADC Channel Selects
The P1SFS0 and P1SFS1 Registers control the
selection of the Port 1 pin functions. When the
P1SFS0 Bit is '0,' the pin functions as a GPIO.
When bits are set to '1,' the pins are configured as
alternate functions. A new P1SFS1 Register se-
lects which of the alternate functions is enabled.
The ADC channel is enabled when the bit in
P1SFS1 is set to '1.'
Note: In the 52-pin package, there is no individual
V_REF pin because V_REF is combined with AV_CC
pin.
Figure 46. 10-Bit ADC
AVREF
AVREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ANALOG
MUX
SELECT
10-BIT SAR ADC
CONTROL
ADC OUT - 10 BITS
ACON REG
ADAT1
REG
ADAT 0 REG
AI07856
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