UPSD33XX Datasheet, PDF (194/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
In MCU I/O mode, Latched Address Out mode,
and Peripheral I/O mode, the pins of Ports A, B, C,
and D become standard CMOS inputs during a re-
set condition. If no external devices are driving
these pins during reset, then these inputs may
float and draw excessive current. If low power con-
sumption is critical during reset, then these floating
inputs should be pulled up externally to V_DD with a
weak (100KΩ minimum) resistor.
In PLD I/O mode, pins of Ports A, B, C, and D may
also float during reset if no external device is driv-
ing them, and if there is no equation specified for
the DPLD or GPLD to make them an output. In this
case, a weak external pull-up resistor (100KΩ min-
imum) should be used on floating pins to avoid ex-
cessive current draw.
The pins on Ports 1, 3, and 4 of the 8032 MCU
module do have weak internal pull-ups and the in-
puts will not float, so no external pull-ups are need-
ed.
Table 121. Function Status During Power-Up Reset, Warm Reset, Power-down Mode
Port Configuration
Power-Up Reset
Warm Reset
APD Power-down Mode
MCU I/O
Pins are in input mode
Pins are in input mode
Pin logic state is
unchanged
PLD I/O
Pin logic is valid after
internal PSD Module
configuration bits are
loaded. Happens long
before RST is de-asserted
Pin logic is valid and is
determined by PLD logic
equations
Pin logic depends on inputs
to PLD (8032 addresses
are blocked from reaching
PLD inputs during power-
down mode)
Latched Address Out Mode Pins are High Impedance
Pins are High Impedance
Pins logic state not defined
since 8032 address signals
are blocked
Peripheral I/O Mode
Pins are High Impedance Pins are High Impedance Pins are High Impedance
JTAG ISP and Debug
JTAG channel is active and JTAG channel is active and JTAG channel is active and
available
available
available
Register
Power-Up Reset
Warm Reset
APD Power-down Mode
PMMR0 and PMMR2
Cleared to 00h
Unchanged
Unchanged
Output of OMC Flip-flops
Cleared to ’0’
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register⁽¹⁾
Initialized with value that
was specified in PSDsoft
Initialized with value that
was specified in PSDsoft
Unchanged
All other csiop registers
Cleared to 00h
Cleared to 00h
Unchanged
Note: 1. VM register Bit 7 (PIO_EN) and Bit 0 (SRAM in 8032 program space) are cleared to zero at power-up and warm reset conditions.
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