UPSD33XX Datasheet, PDF (143/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 78. VM Register (address = csiop + offset E2h)
Bit 7
PIO_EN
Bit 6
Bit 5
Bit 4
Main Flash
XDATA
Space
Bit 3
Secondary
Flash XDATA
Space
Bit 2
Main Flash
Program
Space
Bit 1
Secondary
Flash
Program
Space
Bit 0
SRAM
Program
Space
0 = disable
Peripheral I/O not used
Mode on Port A
not used
0 = RD or WR
cannot
access Main
Flash
0 = RD or WR
cannot
access
Secondary
Flash
0 = PSEN
cannot
access Main
Flash
0 = PSEN
cannot
access
Secondary
Flash
0 = PSEN
cannot
access
SRAM
1 = enable
Peripheral I/O not used
Mode on Port A
not used
1 = RD or WR
can access
Main Flash
1 = RD or WR
can access
Secondary
Flash
1 = PSEN
can access
Main Flash
1 = PSEN
can access
Secondary
Flash
1 = PSEN
can access
SRAM
Note: 1. Default value of Bits 0, 1, 2, 3, and 4 is loaded from Non-Volatile setting as specified from PSDsoft Express upon any reset or power-
up condition. The default value of these bits can be overridden by 8032 at run-time.
2. Default value of Bit 7 is zero upon any reset condition.
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