UPSD33XX Datasheet, PDF (166/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
OMC Mask Registers. There is one OMC Mask
Register for each of the two groups of eight OMCs
shown in Table 88 and Table 89. The OMC mask
registers are used to block loading of data to indi-
vidual OMCs. The default value for the mask reg-
isters is 00h, which allows loading of all OMCs.
When a given bit in a mask register is set to a '1,'
the 8032 is blocked from writing to the associated
OMC flip-flop. For example, suppose that only four
of eight OMCs (MCELLAB0-3) are being used for
a state machine. The user may not want the 8032
write to all the OMCs in MCELLAB because it
would overwrite the state machine registers.
Therefore, the user would want to load the mask
register for MCELLAB with the value 0Fh before
writing OMCs.
Table 88. Output Macrocell MCELLAB Mask Register (address = csiop + offset 22h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
MCELLAB7 MCELLAB6 MCELLAB5 MCELLAB4 MCELLAB3 MCELLAB2 MCELLAB1 MCELLAB0
Note: 1. Default is 00h after any reset condition
2. 1 = block writing to individual macrocell, 0 = allow writing to individual macrocell
Table 89. Output Macrocell MCELLBC Mask Register (address = csiop + offset 23h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
MCELLBC7 MCELLBC6 MCELLBC5 MCELLBC4 MCELLBC3 MCELLBC2 MCELLBC1 MCELLBC0
Note: 1. Default is 00h after any reset condition
2. 1 = block writing to individual macrocell, 0 = allow writing to individual macrocell
Input Macrocells. The GPLD has 20 IMCs, one
for each pin on Port A (80-pin device only), one for
each pin on Port B, and for the four pins on Port C
that are not JTAG pins. The architecture of one in-
dividual IMC is shown in Figure 68., page 167.
IMCs are individually configurable, and they can
strobe a signal coming in from a port pin as a latch
(gated), or as a register (clocked), or the IMC can
pass the signal without strobing, all prior to driving
the signal onto the PLD input bus. Strobing is use-
ful for sampling and debouncing inputs (keypad in-
puts, etc.) before entering the PLD AND-OR
arrays. The outputs of IMCs can be read by the
8032 asynchronously when the 8032 reads the
csiop registers shown in Table 90, Table 91, and
Table 92., page 167. It is possible to read a PSD
Module port pin using one of two different meth-
ods, one method is by reading IMCs as described
here, the other method is using MCU I/O mode de-
scribed in a later section.
The optional IMC clocking or gating signal used to
strobe pin inputs is driven by a product term from
the AND-OR array. There is one clocking or gating
product term available for each group of four
IMCs. Port inputs 0-3 are controlled by one prod-
uct term and 4-7 by another. To specify in PSDsoft
Express the method in which a signal will be
strobed as it enters an IMC for a given input pin on
Port A, B, or C, just specify “PT Clocked Register”
to use a rising edge to clock the incoming signal,
or specify “PT Clock Latch” to use an active high
gate signal to latch the incoming signal. Then de-
fine an equation for the IMC clock (.ld) or the IMC
gate (.le) signal in the “I/O Equations” section.
If the user would like to latch an incoming signal
using the gate signal ALE from the 8032, then in
PSDsoft Express, for a given input pin on Port A,
B, or C, specify “Latched Address” as the pin func-
tion.
If it is desired to pass an incoming signal through
an IMC directly to the AND-OR array inputs with-
out clocking or gating (this is most common), in
PSDsoft Express simply specify “Logic or Ad-
dress” for the input pin function on Port A, B, or C.
166/231