UPSD33XX Datasheet, PDF (155/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Flash Memory Sector Protection. Each Flash
memory sector can be separately protected
against program and erase operations. This mode
can be activated (or deactivated) by selecting this
feature in PSDsoft Express and then programming
through the JTAG Port. Sector protection can be
selected for individual sectors, and the 8032 can-
not override the protection during run-time. The
8032 can read, but not change, sector protection.
Any attempt to program or erase a protected Flash
memory sector is ignored. The 8032 may read the
contents of a Flash sector even when a sector is
protected.
Sector protection status is not read using Flash
memory instruction sequences, but instead this
status is read by the 8032 reading two registers
within csiop address space shown in Table 82 and
Table 83.
Flash Memory Protection During Power-Up.
Flash memory WRITE operations are automatical-
ly prevented while V_DD is ramping up until it rises
above V_LKO voltage threshold at which time Flash
memory WRITE operations are allowed.
PSD Module Security Bit. A programmable se-
curity bit in the PSD Module protects its contents
from unauthorized viewing and copying. The secu-
rity bit is set using PSDsoft Express and pro-
grammed into the PSD Module with JTAG. When
set, the security bit will block access of JTAG pro-
gramming equipment from reading or modifying
the PSD Module Flash memory and PLD configu-
ration. The security bit also blocks JTAG access to
the MCU Module for debugging. The only way to
defeat the security bit is to erase the entire PSD
Module using JTAG (erase is the only JTAG oper-
ation allowed while security bit is set), after which
the device is blank and may be used again. The
8032 MCU will always have access to Flash mem-
ory contents through its 8-bit data bus even while
the security bit is set. The 8032 can read the status
of the security bit at run-time (but it cannot change
it) by reading the csiop register defined in Table
83.
Table 82. Main Flash Memory Protection Register Definition (address = csiop + offset C0h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot
Note: Bit Definitions:
Sec<i>_Prot 1 = Flash memory sector <i> is write protected, 0 = Flash memory sector <i> is not write protected.
Sec0_Prot
Table 83. Secondary Flash Memory Protection/Security Register Definition (csiop + offset C2h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit not used
not used
not used Sec3_Prot Sec2_Prot Sec1_Prot
Note: Security_Bit = 1, device is secured, 0 = not secured
Note: Sec<i>_Prot 1 = Flash memory sector <i> is write protected, 0 = Flash memory sector <i> is not write protected.
Sec0_Prot
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