UPSD33XX Datasheet, PDF(196/231 Page) STMicroelectronics – Fast 8032 MCU with Programmable Logic

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UPSD33XX Datasheet, PDF (196/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

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uPSD33xx

In-System Programming. The ISP function can

use two different configurations of the JTAG inter-

face:

â 4-pin JTAG: TDI, TDO, TCK, TMS

â 6-pin JTAG: Signals above plus TSTAT,

TERR

At power-up, the four basic JTAG signals are all in-

puts, waiting for a command to appear on the

JTAG bus from programming or test equipment.

When the enabling command is received, TDO be-

comes an output and the JTAG channel is fully

functional. The same command that enables the

JTAG channel may optionally enable the two addi-

tional signals, TSTAT and TERR.

4-pin JTAG ISP (default). The four basic JTAG

pins on Port C are enabled for JTAG operation at

all times. These pins may not be used for other I/

O functions. There is no action needed in PSDsoft

Express to configure a device to use 4-pin JTAG,

as this is the default condition. No 8032 firmware

is needed to use 4-pin ISP because all ISP func-

tions are controlled from the external JTAG pro-

gram/test equipment. Figure 81 shows

recommended connections on a circuit board to a

JTAG program/test tool using 4-pin JTAG. It is re-

quired to connect the RST output signal from the

JTAG program/test equipment to the RESET_IN

input on the uPSD33xx. The RST signal is driven

by the equipment with an Open Drain driver, allow-

ing other sources (like a push button) to drive

RESET_IN without conflict.

Note: The recommended pull-up resistors and de-

coupling capacitor are illustrated in Figure 81.

Figure 81. Recommended 4-pin JTAG Connections

CIRCUIT

BOARD

uPSD33XX

TMS - PC0

TCK - PC1

SRAM STBY or I/O - PC2

GENERAL I/O - PC3

GENERAL I/O - PC4

TDI - PC5

TDO - PC6

GENERAL I/O - PC7

RESETIN

100k

typical

JTAG

CONN.

TMS

TCK

GENERAL I/O

SIGNALS

0.01

ÂµF

10k

TDI

TDO

VCC(1,2)

JTAG

Programming

or Test

Equipment

Connects Here

GND

RST(3)

DEBUG

100k

PUSH BUTTON

or ANY OTHER

RESET SOURCE

OPTIONAL

TEST POINT

AI09185

Note: 1. For 5V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 5V system VDD.

2. For 3.3V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 3.3V system VCC.

3. This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than one source to activate RESETIN.

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