UPSD33XX Datasheet, PDF (221/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

Figure 96. Peripheral I/O WRITE Timing
ALE
uPSD33xx
A /D BUS
ADDRESS
DATA OUT
tWLQV (PA)
tWHQZ (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
Table 148. Port A Peripheral Data Mode WRITE Timing (5V PSD Module)
Symbol
Parameter
Conditions
Min
t_WLQV–PA WR to Data Propagation Delay
t_DVQV–PA Data to Port A Data Propagation Delay
(Note 1)
t_WHQZ–PA WR Invalid to Port A Tri-state
Note: 1. Data stable on Port 0 pins to data on Port A.
Table 149. Port A Peripheral Data Mode WRITE Timing (3V PSD Module)
Symbol
Parameter
Conditions
Min
t_WLQV–PA WR to Data Propagation Delay
t_DVQV–PA Data to Port A Data Propagation Delay
(Note 1)
t_WHQZ–PA WR Invalid to Port A Tri-state
Note: 1. Data stable on Port 0 pins to data on Port A.
Table 150. Supervisor Reset and LVD
Symbol
Parameter
Conditions
Min
Typ
t_{RST_LO_IN} Reset Input Duration
1⁽¹⁾
t_{RST_ACTV}
Generated Reset Duration
f_OSC = 40MHz
10⁽²⁾
t_{RST_FIL}
Reset Input Spike Filter
1
V_{RST_HYS}
Reset Input Hysteresis
V_CC = 3.3V
0.1
V_{RST_THRESH} LVD Trip Threshold
V_CC = 3.3V
2.4
2.6
Note: 1. 25µs minimum to abort a Flash memory program or erase cycle in progress.
2. As F_OSC decreases, t_{RST_ACTV} increases. Example: t_{RST_ACTV} = 50ms when F_OSC = 8MHz.
AI06611
Max
Unit
25
ns
22
ns
20
ns
Max
Unit
42
ns
38
ns
33
ns
Max
Unit
µs
ms
µs
V
2.8
V
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