UPSD33XX Datasheet, PDF (192/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
PLD Non-Turbo Mode. The power consumption
and speed of the PLDs are controlled by the Turbo
Bit (Bit 3) in the csiop PMMR0 register. By setting
this bit to logic '1,' the Turbo mode is turned off and
both PLDs consume only stand-by current when
ALL PLD inputs have no transitions for an extend-
ed time (65ns for 5V devices, 100ns for 3.3 V de-
vices), significantly reducing current consumption.
The PLDs will latch their outputs and go to stand-
by, drawing very little current. When Turbo mode
is off, PLD propagation delay time is increased as
shown in the AC specifications for the PSD Mod-
ule. Since this additional propagation delay also
effects the DPLD, the response time of the memo-
ries on the PSD Module is also lengthened by that
same amount of time. If Turbo mode is off, the
user should add an additional wait state to the
8032 BUSCON SFR register if the 8032 clock fre-
quency is higher that a particular value. Please re-
fer to Table 36., page 64 in the MCU Module
section.
The default state of the Turbo Bit is logic '0,' mean-
ing Turbo mode is on by default (after power-up
and reset conditions) until it is turned off by the
8032 writing to PMMR0.
PLD Current Consumption. Figure
85., page 202 and Figure 86., page 202 (5V and
3.3V devices respectively) show the relationship
between PLD current consumption and the com-
posite frequency of all the transitions on PLD in-
puts, indicating that a higher input frequency
results in higher current consumption.
Current consumption of the PLDs have a DC com-
ponent and an AC component. Both need to be
considered when calculating current consumption
for a specific PLD design. When Turbo mode is on,
there is a linear relationship between current and
frequency, and there is a substantial DC current
component consumed by the PSD Module when
there are no transitions on PLD inputs (composite
frequency is zero). The magnitude of this DC cur-
rent component is directly proportional to how
many product terms are used in the equations of
both PLDs. PSDsoft Express generates a “fitter”
report that specifies how many product terms were
used in a design out of a total of 186 available
product terms. Figure 85., page 202 and Figure
86., page 202 both give two examples, one with
100% of the 186 product terms used, and another
with 25% of the 186 product terms used.
Turbo Mode Current Consumption. To deter-
mine the AC current component of the specific
PLD design with Turbo mode on, the user will have
to interpolate from the graph, given the number of
product terms specified in the fitter report, and the
estimated composite frequency of PLD input sig-
nal transitions. For the DC component (y-axis
crossing), the user can calculate the number by
multiplying the number of product terms used
(from fitter report) times the DC current per prod-
uct term specified in the DC specifications for the
PSD Module. The total PLD current usage is the
sum of its AC and DC components.
Non-Turbo Mode Current Consumption. No-
tice in Figure 85., page 202 and Figure
86., page 202 that when Turbo mode is off, the DC
current consumption is “zero” (just standby cur-
rent) when the composite frequency of PLD input
transitions is zero (no input transitions). Now mov-
ing up the frequency axis to consider the AC cur-
rent component, current consumption remains
considerably less than Turbo mode until PLD input
transitions happen so rapidly that the PLDs do not
have time to latch their outputs and go to standby
between the transitions anymore. This is where
the lines converge on the graphs, and current con-
sumption becomes the same for PLD input transi-
tions at this frequency and higher regardless if
Turbo mode is on or off. To determine the current
consumption of the PLDs with Turbo mode off, ex-
trapolate the AC component from the graph based
on number of product terms and input frequency.
The only DC component in non-Turbo mode is the
PSD Module standby current.
The key to reducing PLD current consumption is to
reduce the composite frequency of transitions on
the PLD input bus, moving down the frequency
scale on the graphs. One way to do this is to care-
fully select which signals are entering PLD inputs,
not selecting high frequency signals if they are not
used in PLD equations. Another way is to use PLD
“Blocking Bits” to block certain signals from enter-
ing the PLD input bus.
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