UPSD33XX Datasheet, PDF (214/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Figure 91. Synchronous Clock Mode Timing – PLD
tCH
tCL
CLKIN
INPUT
REGISTERED
OUTPUT
tS
tH
tCO
AI02860
Table 139. CPLD Macrocell Synchronous Clock Mode Timing (5V PSD Module)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo ^Slew
Off _rate⁽¹⁾
Unit
Maximum Frequency
External Feedback
1/(t_S+t_CO)
40.0
MHz
f_MAX
Maximum Frequency
Internal Feedback (f_CNT)
1/(t_S+t_CO–10)
66.6
MHz
Maximum Frequency
Pipelined Data
1/(t_CH+t_CL)
83.3
MHz
t_S Input Setup Time
12
+ 2 + 10
ns
t_H Input Hold Time
0
ns
t_CH Clock High Time
Clock Input
6
ns
t_CL Clock Low Time
Clock Input
6
ns
t_CO Clock to Output Delay
Clock Input
13
– 2 ns
t_ARD CPLD Array Delay
Any macrocell
11
+2
ns
t_{MIN Minimum Clock Period}⁽²⁾
t_CH+t_CL
12
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) t_CLCL = t_CH + t_CL.105
3.
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