UPSD33XX Datasheet, PDF (82/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Multiprocessor Communications. Modes 2 and
3 have a special provision for multiprocessor com-
munications. In these modes, 9 data bits are re-
ceived. The 9th one goes into bit RB8, then comes
a stop bit. The port can be programmed such that
when the stop bit is received, the UART interrupt
will be activated only if bit RB8 = 1. This feature is
enabled by setting bit SM2 in SCON. A way to use
this feature in multi-processor systems is as fol-
lows: When the master processor wants to trans-
mit a block of data to one of several slaves, it first
sends out an address byte which identifies the tar-
get slave. An address byte differs from a data byte
in that the 9th bit is 1 in an address byte and 0 in a
data byte. With SM2 = 1, no slave will be interrupt-
ed by a data byte. An address byte, however, will
interrupt all slaves, so that each slave can exam-
ine the received byte and see if it is being ad-
dressed. The addressed slave will clear its SM2 bit
and prepare to receive the data bytes that will be
coming. The slaves that were not being addressed
leave their SM2 bits set and go on about their busi-
ness, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1, SM2
can be used to check the validity of the stop bit. In
a Mode 1 reception, if SM2 = 1, the receive inter-
rupt will not be activated unless a valid stop bit is
received.
Serial Port Control Registers
The SFR SCON0 controls UART0, and SCON1
controls UART1, shown in Table 45 and Table 46.
These registers contain not only the mode selec-
tion bits, but also the 9th data bit for transmit and
receive (bits TB8 and RB8), and the UART Inter-
rupt flags, TI and RI.
Table 45. SCON0: Serial Port UART0 Control Register (SFR 98h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Details
Bit
Symbol
R/W
Definition
7
SM0
R,W
Serial Mode Select, See Table 44., page 81. Important, notice bit order
of SM0 and SM1.
[SM0:SM1] = 00b, Mode 0
6
SM1
R,W
[SM0:SM1] = 01b, Mode 1
[SM0:SM1] = 10b, Mode 2
[SM0:SM1] = 11b, Mode 3
Serial Multiprocessor Communication Enable.
Mode 0: SM2 has no effect but should remain 0.
5
SM2
R,W
Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI active if stop
bit = 1.
Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th bit is
ignored. If SM2=1, RI active when 9th bit = 1.
Receive Enable.
4
REN
R,W
If REN=0, UART reception disabled. If REN=1, reception is enabled
3
TB8
R,W
TB8 is assigned to the 9th transmission bit in Mode 2 and 3. Not used in
Mode 0 and 1.
Mode 0: RB8 is not used.
2
RB8
R,W
Mode 1: If SM2 = 0, the RB8 is the level of the received stop bit.
Mode 2 and 3: RB8 is the 9th data bit that was received in Mode 2 and
3.
Transmit Interrupt flag.
1
TI
R,W
Causes interrupt at end of 8th bit time when transmitting in Mode 0, or at
beginning of stop bit transmission in other modes. Must clear flag with
firmware.
Receive Interrupt flag.
0
RI
R,W
Causes interrupt at end of 8th bit time when receiving in Mode 0, or
halfway through stop bit reception in other modes (see SM2 for
exception). Must clear this flag with firmware.
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