UPSD33XX Datasheet, PDF (197/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
6-pin JTAG ISP (optional). The optional signals
TSTAT and TERR are programming status flags
that can reduce programming time by as much as
30% compared to 4-pin JTAG because this status
information does not have to be scanned out of the
device serially. TSTAT and TERR must be used
as a pair for 6-pin JTAG operation.
– TSTAT (pin PC3) indicates when
programming of a single Flash location is
complete. Logic 1 = Ready, Logic 0 = busy.
– TERR (pin PC4) indicates if there was a Flash
programming error. Logic 1 = no error,
Logic 0 = error.
The pin functions for PC3 and PC4 must be select-
ed as “Dedicated JTAG - TSTAT” and “Dedicated
JTAG - TERR” in PSDsoft Express to enable 6-pin
JTAG ISP.
No 8032 firmware is needed to use 6-pin ISP be-
cause all ISP functions are controlled from the ex-
ternal JTAG program/test equipment.
TSTAT and TERR are functional only when JTAG
ISP operations are occurring, which means they
are non-functional during JTAG debugging of the
8032 on the MCU Module.
Programming times vary depending on the num-
ber of locations to be programmed and the JTAG
programming equipment, but typical JTAG ISP
programming times are 10 to 25 seconds using 6-
pin JTAG. The signals TSTAT and TERR are not
included in the IEEE 1149.1 specification.
Figure 82., page 198 shows recommended con-
nections on a circuit board to a JTAG program/test
tool using 6-pin JTAG. It is required to connect the
RST output signal from the JTAG program/test
equipment to the RESET_IN input on the
uPSD33xx. The RST signal is driven by the equip-
ment with an Open Drain driver, allowing other
sources (like a push button) to drive RESET_IN
without conflict.
Note: The recommended pull-up resistors and de-
coupling capacitor are illustrated in Figure 82.
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