UPSD33XX Datasheet, PDF (162/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Output Macrocell. The GPLD has 16 OMCs. Ar-
chitecture of one individual OMC is shown in Fig-
ure 66. OMCs can be used for internal node
feedback (buried registers to build shift registers,
etc.), or their outputs may be routed to external
port pins. The user can choose any mixture of
OMCs used for buried functions and OMCs used
to drive port pins.
Referring to Figure 66, for each OMC there are na-
tive product terms available from the AND-OR Ar-
ray to form logic, and also borrowed product terms
are available (if unused) from other OMCs. The
polarity of the final product term output is con-
trolled by the XOR gate. Each OMC can imple-
ment sequential logic using the flip-flop element,
or combinatorial logic when bypassing the flip-flop
as selected by the output multiplexer. An OMC
output can drive a port pin through the OMC Allo-
cator, it can also drive the 8032 data bus, and also
it can drive a feedback path to the AND-OR Array
inputs, all at the same time.
The flip-flop in each OMC can be synthesized as a
D, T, JK, or SR type in PSDsoft Express. OMC flip-
flops are specified using PSDsoft Express in the
“User Defined Nodes” section of the Design Assis-
tant. Each flip-flop’s clock, preset, and clear inputs
may be driven individually from a product term of
the AND-OR Array, defined by equations in PSD-
soft Express for signals *. c, *.pr, and *.re respec-
tively. The preset and clear inputs on the flip-flops
are level activated, active-high logic signals. The
clock inputs on the flip-flops are rising-edge logic
signals.
Optionally, the signal CLKIN (pin PD1) can be
used for a common clock source to all OMC flip-
flops. Each flip-flop is clocked on the rising edge.
A common clock is specified in PSDsoft Express
by assigning the function “Common Clock Input”
for pin PD1 in the Pin Definition section, and then
choosing the signal CLKIN when specifying the
clock input (*.c) for individual flip-flops in the “User
Defined Nodes” section.
Figure 66. Detail of a Single OMC
PRODUCT TERMS
FROM OTHER
OMCs
FROM AND-OR ARRAY
FROM AND-OR ARRAY
FROM PLD INPUT BUS
FROM AND-OR ARRAY
BORROWED LENDED
PTs
PTs
PT ALLOCATOR,
DRAWS FROM LOCAL
AND GLOBAL UNUSED
PRODUCT TERMS.
PSDsoft DICTATES.
PT PRESET (.PR)
ALLOCATED PTs
NATIVE PTs
POLARITY
SELECT,
PSDsoft
GLOBAL CLOCK (CLKIN)
PT CLOCK (.C)
MCU OVERRIDES
PT PRESET AND
CLR DURING
MCU WRITE
MUX
PRE
D
Q
M
U
X
CLR
DATA BIT FROM 8032
INDICATES MCU WRITE
TO PARTICULAR CSIO
OMC REGISTER
MCU READ OF
PARTICULAR CSIOP
OMC REGISTER
DATA BIT TO 8032
O
U^M
T^U
X
PSDsoft
OMC
OUTPUT
OMC
ALLO-
CATOR
FROM AND-OR ARRAY
TO PLD INPUT BUS
PT CLEAR (.RE)
NODE FEEDBACK (.FB)
PSDsoft
MUX
OUTPUT MACROCELL (OMC)
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