UPSD33XX Datasheet, PDF (189/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Automatic Power-Down (APD). The APD unit
shown in Figure 63., page 157 puts the PSD Mod-
ule into power-down mode by monitoring the activ-
ity of the 8032 Address Latch Enable (ALE) signal.
If the APD unit is enabled by writing a logic ’1’ to
Bit 1 of the csiop PMMR0 register, and if ALE sig-
nal activity has stopped (8032 in sleep mode),
then the four-bit APD counter starts counting up. If
the ALE signal remains inactive for 15 clock peri-
ods of the CLKIN signal (pin PD1), then the APD
counter will reach maximum count and the power
down indicator signal (PDN) goes to logic ’1’ forc-
ing the PSD Module into power-down mode. Dur-
ing this time, all buffers on the PSD Module for
8032 address and data signals are disabled in sil-
icon, preventing the PSD Module memories from
waking up from stand-by mode, even if noise or
other devices are driving the address lines. The
PLDs will also stay in standby mode if the PLDs
are in non-Turbo mode and if all other PLD inputs
(non-address signals) are static.
However, if the ALE signal has a transition before
the APD counter reaches max count, the APD
counter is cleared to zero and the PDN signal will
not go active, preventing power-down mode. To
prevent unwanted APD time-outs during normal
8032 operation (not sleeping), it is important to
choose a clock frequency for CLKIN that will NOT
produce 15 or more pulses within the longest peri-
od between ALE transitions. A 32768 Hz clock sig-
nal is quite often an ideal frequency for CLKIN and
APD, and this frequency is often available on ex-
ternal supervisor or real-time clock devices.
The “PDN” power-down indicator signal is avail-
able to the PLD input bus to use in any PLD equa-
tions if desired. The user may want to send this
signal as a PLD output to an external device to in-
dicate the PSD Module is in power-down mode.
PSDsoft Express automatically includes the
“PDN” signal in the DPLD chip select equations for
FSx, CSBOOTx, RS0, and CSIOP.
The following should be kept in mind when the
PSD Module is in power-down mode:
– 8032 address and data bus signals are
blocked from all memories and both PLDs.
– The PSD Module comes out of power-down
mode when: ALE starts pulsing again, or the
CSI input on pin PD2 transitions from logic ’1’
to logic '0,' or the PSD Module reset signal,
RST, transitions from logic ’0’ to logic '1.'
– Various signals can be blocked (prior to
power-down mode) from entering the PLDs by
using “blocking bits” in csiop PMMR registers.
– All memories enter standby mode, and the
state of the PLDs and I/O Ports are
unchanged (if no PLD inputs change). Table
121., page 194 shows the effects of power-
down mode on I/O pins while in various
operating modes.
– The 8032 Ports 1,3, and 4 on the MCU Module
are not affected at all by power-down mode in
the PSD Module.
– Power-down standby current given in the AC
specifications for PSD Module assume there
are no transitions on any unblocked PLD
input, and there are no output pins driving any
loads.
The APD counter will count whenever Bit 1 of
csiop PMMR0 register is set to logic '1,' and when
the ALE signal is steady at either logic ’1’ or logic
’0’ (not transitioning). Figure 79., page 191 shows
the flow leading up to power-down mode. The only
action required in PSDsoft Express to enable APD
mode is to select the pin function “Common Clock
Input, CLKIN” before programming with JTAG.
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