UPSD33XX Datasheet, PDF (87/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
More About UART Mode 1
Refer to the block diagram in Figure 30., page 88,
and timing diagram in Figure 31., page 88.
Transmission is initiated by any instruction which
writes to SBUF. At the end of a write operation to
SBUF, a '1' is loaded into the 9th position of the
transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission ac-
tually starts at the end of the MCU the machine cy-
cle following the next rollover in the divide-by-16
counter. Thus, the bit times are synchronized to
the divide-by-16 counter, not to the writing of
SBUF. Transmission begins with activation of
SEND which puts the start bit at pin TxD. One bit
time later, DATA is activated, which enables the
output bit of the transmit shift register to pin TxD.
The first shift pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked
in from the left. When the MSB of the data byte is
at the output position of the shift register, then the
1 that was initially loaded into the 9th position is
just to the left of the MSB, and all positions to the
left of that contain zeros. This condition flags the
TX Control unit to do one last shift and then deac-
tivates SEND, and sets the interrupt flag, TI. This
occurs at the 10th divide-by-16 rollover after a
write to SBUF.
Reception is initiated by a detected 1-to-0 transi-
tion at the pin RxD. For this purpose RxD is sam-
pled at a rate of 16 times whatever baud rate has
been established. When a transition is detected,
the divide-by-16 counter is immediately reset, and
1FFH is written into the input shift register. Reset-
ting the divide-by-16 counter aligns its rollovers
with the boundaries of the incoming bit times. The
16 states of the counter divide each bit time into
16ths. At the 7th, 8th, and 9th counter states of
each bit time, the bit detector samples the value of
RxD. The value accepted is the value that was
seen in at least 2 of the 3 samples. This is done for
noise rejection. If the value accepted during the
first bit time is not '0,' the receive circuits are reset
and the unit goes back to looking for another '1'-to-
'0' transition. This is to provide rejection of false
start bits. If the start bit proves valid, it is shifted
into the input shift register, and reception of the re-
set of the rest of the frame will proceed. As data
bits come in from the right, '1s' shift out to the left.
When the start bit arrives at the left-most position
in the shift register (which in mode 1 is a 9-bit reg-
ister), it flags the RX Control unit to do one last
shift, load SBUF and RB8, and set the receive in-
terrupt flag RI. The signal to load SBUF and RB8,
and to set RI, will be generated if, and only if, the
following conditions are met at the time the final
shift pulse is generated:
1. RI = 0, and
2. Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions are not met, the re-
ceived frame is irretrievably lost. If both conditions
are met, the stop bit goes into RB8, the 8 data bits
go into SBUF, and RI is activated. At this time,
whether the above conditions are met or not, the
unit goes back to looking for a '1'-to-'0' transition
on pin RxD.
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