UPSD33XX Datasheet, PDF (149/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Instr.
Bus
Sequence Cycle 1
Bus
Cycle 2
Bus
Bus
Bus
Cycle 3 Cycle 4 Cycle 5
Bus
Cycle 6
Bus
Cycle 7
Link
Reset
Flash
Write F0h to
address that
activates
FSx or
CSBOOTx
in desired
array.
(command)
Reset
Flash, page
154
Note: 1. All values are in hexadecimal, X = Don’t care
2. 8032 addresses A12 through A15 are “Don’t care” during the instruction sequence decoding. Only address bits A0-A11 are used
during decoding of Flash memory instruction sequences. The individual sector select signal (FS0 - FS7 or CSBOOT0-CSBOOT3)
which is active during the instruction sequence determines the complete address.
3. Directing this command to any individual sector within a Flash memory array will invoke the bulk erase of all Flash memory sectors
within that array.
Reading Flash Memory. Under typical condi-
tions, the 8032 may read the Flash memory using
READ operations (READ bus cycles) just as it
would a ROM or RAM device. Alternately, the
8032 may use READ operations to obtain status
information about a Program or Erase operation
that is currently in progress. The following sections
describe the kinds of READ operations.
Read Memory Contents. Flash memory is
placed in the Read Array mode after Power-up, af-
ter a PSD Module reset event, or after receiving a
Reset Flash memory instruction sequence from
the 8032. The 8032 can read Flash memory con-
tents using standard READ bus cycles anytime the
Flash array is in Read Array mode. Flash memo-
ries will always be in Read Array mode when the
array is not actively engaged in a program or erase
operation.
Reading the Erase/Program Status Bits. The
Flash arrays provide several status bits to be used
by the 8032 to confirm the completion of an erase
or program operation on Flash memory, shown in
Table 81., page 150. The status bits can be read
as many times as needed until an operation is
complete.
The 8032 performs a READ operation to obtain
these status bits while an erase or program oper-
ation is being executed by the state machine in-
side each Flash memory array.
Data Polling Flag (DQ7). While programming ei-
ther Flash memory, the 8032 may read the Data
Polling Flag Bit (DQ7), which outputs the comple-
ment of the D7 Bit of the byte being programmed
into Flash memory. Once the program operation is
complete, DQ7 is equal to D7 of the byte just pro-
grammed into Flash memory, indicating the pro-
gram cycle has completed successfully. The
correct select signal, FSx or CSBOOTx, must be
active during the entire polling procedure.
Polling may also be used to indicate when an
erase operation has completed. During an erase
operation, DQ7 is '0.' After the erase is complete
DQ7 is '1.' The correct select signal, FSx or CS-
BOOTx, must be active during the entire polling
procedure.
DQ7 is valid after the fourth instruction byte
WRITE operation (for program instruction se-
quence) or after the sixth instruction byte WRITE
operation (for erase instruction sequence).
If all Flash memory sectors to be erased are pro-
tected, DQ7 is reset to ’0’ for about 100µs, and
then DQ7 returns to the value of D7 of the previ-
ously addressed byte. No erasure is performed.
Toggle Flag (DQ6). The Flash memories offer an
alternate way to determine when a Flash memory
program operation has completed. During the pro-
gram operation and while the correct sector select
FSx or CSBOOTx is active, the Toggle Flag Bit
(DQ6) toggles from '0' to '1' and '1' to ’0’ on subse-
quent attempts to read any byte of the same Flash
array.
When the internal program operation is complete,
the toggling stops and the data read on the data
bus D0-7 is the actual value of the addressed
memory byte. The device is now accessible for a
new READ or WRITE operation. The operation is
finished when two successive READs yield the
same value for DQ6.
DQ6 may also be used to indicate when an erase
operation has completed. During an erase opera-
tion, DQ6 will toggle from '0' to '1' and '1' to ’0’ until
the erase operation is complete, then DQ6 stops
toggling. The erase is finished when two succes-
sive READs yield the same value of DQ6. The cor-
rect sector select signal, FSx or CSBOOTx, must
be active during the entire procedure.
DQ6 is valid after the fourth instruction byte
WRITE operation (for program instruction se-
quence) or after the sixth instruction byte WRITE
operation (for erase instruction sequence).
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