UPSD33XX Datasheet, PDF (69/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

STANDARD 8032 TIMER/COUNTERS
There are three 8032-style 16-bit Timer/Counter
registers (Timer 0, Timer 1, Timer 2) that can be
configured to operate as timers or event counters.
There are two additional 16-bit Timer/Counters in
the Programmable Counter Array (PCA), seePCA
Block, page 123 for details.
Standard Timer SFRs
Timer 0 and Timer 1 have very similar functions,
and they share two SFRs for control:
■ TCON (Table 39., page 70)
■ TMOD (Table 40., page 72).
Timer 0 has two SFRs that form the 16-bit counter,
or that can hold reload values, or that can scale
the clock depending on the timer/counter mode:
■ TH0 is the high byte, address 8Ch
■ TL0 is the low byte, address 8Ah
Timer 1 has two similar SFRs:
■ TH1 is the high byte, address 8Dh
■ TL1 is the low byte, address 8Bh
Timer 2 has one control SFR:
■ T2CON (Table 41., page 75)
Timer 2 has two SFRs that form the 16-bit counter,
and perform other functions:
■ TH2 is the high byte, address CDh
■ TL2 is the low byte, address CCh
Timer 2 has two SFRs for capture and reload:
■ RCAP2H is the high byte, address CBh
■ RCAP2L is the low byte, address CAh
uPSD33xx
Clock Sources
When enabled in the “Timer” function, the Regis-
ters THx and TLx are incremented every 1/12 of
the oscillator frequency (f_OSC). This timer clock
source is not effected by MCU clock dividers in the
CCON0, stalls from PFQ/BC, or bus transfer cy-
cles. Timers are always clocked at 1/12 of f_OSC.
When enabled in the “Counter” function, the Reg-
isters THx and TLx are incremented in response to
a 1-to-0 transition sampled at their corresponding
external input pin: pin C0 for Timer 0; pin C1 for
Timer 1; or pin T2 for Timer 2. In this function, the
external clock input pin is sampled by the counter
at a rate of 1/12 of f_OSC. When a logic '1' is deter-
mined in one sample, and a logic '0' in the next
sample period, the count is incremented at the
very next sample period (period1: sample=1,
period2: sample=0, period3: increment count
while continuing to sample). This means the max-
imum count rate is 1/24 of the f_OSC. There are no
restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled
at least once before it changes, it should be active
for at least one full sample period (12 / f_OSC, sec-
onds). However, if MCU_CLK is divided by the
SFR CCON0, then the sample period must be cal-
culated based on the resultant, longer, MCU_CLK
frequency. In this case, an external clock signal on
pins C0, C1, or T2 should have a duration longer
than one MCU machine cycle, t_{MACH_CYC}. The
section, Watchdog Timer, WDT, page 66 explains
how to estimate t_{MACH_CYC}.
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