UPSD33XX Datasheet, PDF (217/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 142. CPLD Macrocell Asynchronous Clock Mode Timing (3V PSD Module)
Symbol
Parameter
Conditions
Min
Max
PT Turbo Slew
Aloc Off Rate
Unit
Maximum Frequency
External Feedback
1/(t_SA+t_COA)
21.7
MHz
f_MAXA
Maximum Frequency
Internal Feedback (f_CNTA)
1/(t_SA+t_COA–10)
27.8
MHz
Maximum Frequency
Pipelined Data
1/(t_CHA+t_CLA)
33.3
MHz
t_SA Input Setup Time
10
+ 4 + 15
ns
t_HA Input Hold Time
12
ns
t_CHA Clock High Time
17
+ 15
ns
t_CLA Clock Low Time
13
+ 15
ns
t_COA Clock to Output Delay
31
+ 15 – 6 ns
t_ARD CPLD Array Delay
Any macrocell
20
+4
ns
t_MINA Minimum Clock Period
1/f_CNTA
36
ns
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