UPSD33XX Datasheet, PDF (160/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
General PLD (GPLD). The GPLD is used to cre-
ate general system logic. Figure 63., page 157
shows the architecture of the entire GPLD, and
Figure 65., page 161 shows the relationship be-
tween one OMC, one IMC, and one I/O port pin,
which is representative of pins on Ports A, B, and
C. It is important to understand how these ele-
ments work together. A more detailed description
will follow for the three major blocks (OMC, IMC, I/
O Port) shown in Figure 65. Figure 65 also shows
which csiop registers to access for various PLD
and I/O functions.
The GPLD contains:
■ 16 Output Macrocells (OMC)
■ 20 Input Macrocells (IMC)
■ OMC Allocator
■ Product Term Allocator inside each OMC
■ AND-OR Array capable of generating up to
137 product terms
■ Three I/O Ports, A, B, and C
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