UPSD33XX Datasheet, PDF (102/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
I²C Interface Status Register (S1STA)
The S1STA register provides status regarding im-
mediate activity and the current state of operation
on the I²C bus. All bits in this register are read-only
except bit 5, INTR, which is the interrupt flag.
Interrupt Conditions. If the I²C interrupt is en-
abled (EI²C = 1 in SFR named IEA, and EA =1 in
SFR named IE), and the SIOE is initialized, then
an interrupt is automatically generated when any
one of the following five events occur:
– When the SIOE receives an address that
matches the contents of the SFR, S1ADR.
Requirements: SIOE is in Slave Mode, and bit
AA = 1 in the SFR S1CON.
– When the SIOE receives General Call
address. Requirments: SIOE is in Slave Mode,
bit AA = 1 in the SFR S1CON
– When a complete data byte has been received
or transmitted by the SIOE while in Master
mode. The interrupt will occur even if the
Master looses arbitration.
– When a complete data byte has been received
or transmitted by the SIOE while in selected
Slave mode.
– A STOP condition on the bus has been
recognized by the SIOE while in selected
Slave mode.
Selected Slave mode means the device address
sent by the Master device at the beginning of the
current data transfer matched the address stored
in the S1ADR register.
If the I²C interrupt is not enabled, the MCU may
poll the INTR flag in S1STA.
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