UPSD33XX Datasheet, PDF (188/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 117. Power Management Mode Register PMMR0 (address = csiop + offset B0h)
Bit 0
X
0 Not used, and should be set to zero.
Bit 1 APD Enable
0 Automatic Power Down (APD) counter is disabled.
1 APD counter is enabled
Bit 2
X
0 Not used, and should be set to zero.
Bit 3
PLD Turbo
Disable
0 = on PLD Turbo mode is on
1 = off PLD Turbo mode is off, saving power.
Bit 4
Blocking Bit,
CLKIN to
PLDs⁽¹⁾
0 = on
CLKIN (pin PD1) to the PLD Input Bus is not blocked. Every transition of CLKIN
powers-up the PLDs.
1 = off
CLKIN input to PLD Input Bus is blocked, saving power. But CLKIN still goes to APD
counter.
Bit 5
Blocking Bit, ^{0 = on CLKIN input is not blocked from reaching all OMC’s common clock inputs.}
CLKIN to
OMCs Only⁽¹⁾
1 = off
CLKIN input to common clock of all OMCs is blocked, saving power. But CLKIN still
goes to APD counter and all PLD logic besides the common clock input on OMCs.
Bit 6
X
0 Not used, and should be set to zero.
Bit 7
X
0 Not used, and should be set to zero.
Note: All the bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers.
1. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.
Table 118. Power Management Mode Register PMMR2 (address = csiop + offset B4h)
Bit 0
X
0 Not used, and should be set to zero.
Bit 1
X
0 Not used, and should be set to zero.
Blocking Bit, ^{0 = on 8032 WR input to the PLD Input Bus is not blocked.}
Bit 2 _{WR to PLDs(1) 1 = off 8032 WR input to PLD Input Bus is blocked, saving power.}
Blocking Bit, ^{0 = on 8032 RD input to the PLD Input Bus is not blocked.}
Bit 3 _{RD to PLDs(1) 1 = off 8032 RD input to PLD Input Bus is blocked, saving power.}
Bit 4
Blocking Bit,
PSEN to
PLDs⁽¹⁾
0 = on 8032 PSEN input to the PLD Input Bus is not blocked.
1 = off 8032 PSEN input to PLD Input Bus is blocked, saving power.
Bit 5
Blocking Bit,
ALE to
PLDs⁽¹⁾
0 = on 8032 ALE input to the PLD Input Bus is not blocked.
1 = off 8032 ALE input to PLD Input Bus is blocked, saving power.
Bit 5
Blocking Bit,
PC7 to
PLDs⁽¹⁾
0 = on Pin PC7 input to the PLD Input Bus is not blocked.
1 = off Pin PC7 input to PLD Input Bus is blocked, saving power.
Bit 7
X
0 Not used, and should be set to zero.
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers.
1. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.
Table 119. Power Management Mode Register PMMR3 (address = csiop + offset C7h)
Bit 0
X
0 Not used, and should be set to zero.
Bit 1 FORCE_PD 0 = off APD counter will cause Power-Down Mode if APD is enabled.
1 = on Power-Down mode will be entered immediately regardless of APD activity.
Bit 3-7
X
0 Not used, and should be set to zero.
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers.
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