UPSD33XX Datasheet, PDF (222/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 151. V_STBYON Definitions Timing (5V, 3V PSD Modules)
Symbol
Parameter
Conditions
t_BVBH
V_STBY Detection to V_STBYON Output High
(Note 1)
t_BXBL
V_STBY Off Detection to V_STBYON Output
Low
(Note 1)
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.
Figure 97. ISC Timing
TCK
t_ISCCH
t _ISCCL
t _ISCPSU t_ISCPH
Min
Typ
Max Unit
20
µs
20
µs
TDI/TMS
t _ISCPZV
t _ISCPCO
ISC OUTPUTS/TDO
t_ISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 152. ISC Timing (5V PSD Module)
Symbol
Parameter
t_ISCCF Clock (TCK, PC1) Frequency (except for PLD)
t_ISCCH Clock (TCK, PC1) High Time (except for PLD)
t_ISCCL Clock (TCK, PC1) Low Time (except for PLD)
t_ISCCFP Clock (TCK, PC1) Frequency (PLD only)
t_ISCCHP Clock (TCK, PC1) High Time (PLD only)
t_ISCCLP Clock (TCK, PC1) Low Time (PLD only)
t_ISCPSU ISC Port Set Up Time
t_ISCPH ISC Port Hold Up Time
t_ISCPCO ISC Port Clock to Output
t_ISCPZV ISC Port High-Impedance to Valid Output
t_ISCPVZ ISC Port Valid Output to High-Impedance
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.
2. For Program or Erase PLD only.
Conditions
Min
(Note 1)
(Note 1)
23
(Note 1)
23
(Note 2)
(Note 2)
90
(Note 2)
90
7
5
Max
Unit
20
MHz
ns
ns
5
MHz
ns
ns
ns
ns
21
ns
21
ns
21
ns
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