UPSD33XX Datasheet, PDF (125/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
PCA Clock Selection
The clock input to the 16-bit up counter in the PCA
block is user-programmable. The three clock
sources are:
– PCA Prescaler Clock (PCA0CLK, PCA1CLK)
– Timer 0 Overflow
– External Clock, Pin P4.3 or P4.7
The clock source is selected in the configuration
register PCACON. The Prescaler output clock
PCACLK is the f_OSC divided by the divisor which is
specified in the CCON2 or CCON3 Register.
When External Clock is selected, the maximum
clock frequency should not exceed f_OSC/4.
Table 68. CCON2 Register Bit Definition (SFR 0FBh, Reset Value 10h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
PCA0CE PCA0PS3 PCA0PS2 PCA0PS1
Details
Bit
Symbol
R/W
Definition
PCA0 Clock Enable
4
PCA0CE
R/W
0 = PCA0CLK is disabled
1 = PCA0CLK is enabled (default)
PCA0 Prescaler
3:0
PCA0PS
[3:0]
R/W
f_PCA0CLK = f_OSC / (2 ^ PCA0PS[3:0])
Divisor range: 1, 2, 4, 8, 16... 16384, 32768
Bit 0
PCA0PS0
Table 69. CCON3 Register Bit Definition (SFR 0FCh, Reset Value 10h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
PCA1CE PCA1PS3 PCA1PS2 PCA1PS1
Details
Bit
Symbol
R/W
Definition
PCA1 Clock Enable
4
PCA1CE
R/W
0 = PCA1CLK is disabled
1 = PCA1CLK is enabled (default)
PCA1 Prescaler
3:0
PCA1PS
[3:0]
R/W
f_PCA1CLK = f_OSC / (2 ^ PCA1PS[3:0])
Divisor range: 1, 2, 4, 8, 16... 16384, 32768
Bit 0
PCA1PS0
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