UPSD33XX Datasheet, PDF (33/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

Table 7. Logical Instruction Set
Mnemonic⁽¹⁾
and Use
Description
ANL
A, Rn
AND register to ACC
ANL
A, direct
AND direct byte to ACC
ANL
A, @Ri
AND indirect SRAM to ACC
ANL
A, #data
AND immediate data to ACC
ANL
direct, A
AND ACC to direct byte
ANL
direct, #data
AND immediate data to direct byte
ORL
A, Rn
OR register to ACC
ORL
A, direct
OR direct byte to ACC
ORL
A, @Ri
OR indirect SRAM to ACC
ORL
A, #data
OR immediate data to ACC
ORL
direct, A
OR ACC to direct byte
ORL
direct, #data
OR immediate data to direct byte
SWAP
A
Swap nibbles within the ACC
XRL
A, Rn
Exclusive-OR register to ACC
XRL
A, direct
Exclusive-OR direct byte to ACC
XRL
A, @Ri
Exclusive-OR indirect SRAM to ACC
XRL
A, #data
Exclusive-OR immediate data to ACC
XRL
direct, A
Exclusive-OR ACC to direct byte
XRL
direct, #data
Exclusive-OR immediate data to direct byte
CLR
A
Clear ACC
CPL
A
Compliment ACC
RL
A
Rotate ACC left
RLC
A
Rotate ACC left through the carry
RR
A
Rotate ACC right
RRC
A
Rotate ACC right through the carry
Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.
uPSD33xx
Length/Cycles
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
2 byte/1 cycle
3 byte/2 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
2 byte/1 cycle
3 byte/2 cycle
1 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
2 byte/1 cycle
3 byte/2 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
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