UPSD33XX Datasheet, PDF (104/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
I²C Data Shift Register (S1DAT)
The S1ADR register (Table 53) holds a byte of se-
rial data to be transmitted or it holds a serial byte
that has just been received. The MCU may access
S1DAT while the SIOE is not in the process of
shifting a byte (the INTR flag indicates shifting is
complete).
While transmitting, bytes are shifted out MSB first,
and when receiving, bytes are shifted in MSB first,
through the Acknowledge Bit register as shown in
Figure 40., page 99.
Bus Wait Condition. After the SIOE finishes re-
ceiving a byte in Receive mode, or transmitting a
byte in Transmit mode, the INTR flag (in S1STA)
is set and automatically a wait condition is im-
posed on the I²C bus (SCL held low by SIOE). In
Transmit mode, this wait condition is released as
soon as the MCU writes any byte to S1DAT. In Re-
ceive mode, the wait condition is released as soon
as the MCU reads the S1DAT register.
This method allows the user to handle transmit
and receive operations within an interrupt service
routine. The SIOE will automatically stall the I²C
bus at the appropriate time, giving the MCU time
to get the next byte ready to transmit or time to
read the byte that was just received.
Table 53. S1DAT: I²C Data Shift register (SFR DEh, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S1DAT[7:0]
Details
Bit
Symbol
R/W
Function
7:0
S1DAT[7:0]
R/W
Holds the data byte to be transmitted in Transmit mode, or it holds the
data byte received in Receiver mode.
I²C Address Register (S1ADR)
The S1ADR register (Table 54) holds the 7-bit de-
vice address used when the SIOE is operating as
a Slave. When the SIOE receives an address from
a Master, it will compare this address to the con-
tents of S1ADR, as shown in Figure 40., page 99.
If the 7 bits match, the INTR Interrupt flag (in
S1STA) is set, and the ADDR Bit (in S1CON) is
set. The SIOE cannot modify the contents S1ADR,
and S1ADR is not used during Master mode.
Table 54. S1ADR: I²C Address register (SFR DFh, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
–
Details
Bit
Symbol
R/W
Function
7:1
SLA[6:0]
R/W
Stores desired 7-bit device address, used when SIOE is in Slave mode.
0
–
–
Not used
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