UPSD33XX Datasheet, PDF (137/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Each I/O pin on the PSD Module can be individu-
ally configured for different functions on a pin-by-
pin basis (Figure 69., page 169). Following are the
available functions on PSD Module I/O pins.
– MCU I/O: 8032 controls the output state of
each port pin or it reads input state of each
port pin, by accessing csiop registers at run-
time. The direction (in or out) of each pin is
also controlled by csiop registers at run-time.
– PLD I/O: PSDsoft Express logic equations
and pin configuration selections determine if
pins are connected to OMC outputs or IMC
inputs. This is a static and non-volatile
configuration. Port pins connected to PLD
outputs can no longer be driven by the 8032
using MCU I/O output mode.
– Latched MCU Address Output: Port A or
Port B can output de-multiplexed 8032
address signals A0 - A7 on a pin-by-pin basis
as specified in csiop registers at run-time. In
addition, Port B can also be configured to
output de-multiplexed A8-A15 in PSDsoft
Express.
– Data Bus Repeater: Port A can bi-
directionally buffer the 8032 data bus (de-
multiplexed) for a specified address range in
PSDsoft Express. This is referred to as
Peripheral I/O Mode in this document.
– Open Drain Outputs: Some port pins can
function as open-drain as specified in csiop
registers at run-time.
– Pins on Port D can be used for external chip-
select outputs originating from the DPLD,
without consuming OMC resources within the
GPLD.
JTAG Port. In-System Programming (ISP) can
be performed through the JTAG signals on Port C.
This serial interface allows programming of the en-
tire PSD Module device or subsections of the PSD
Module (for example, only Flash memory but not
the PLDs) without the participation of the 8032. A
blank uPSD33xx device soldered to a circuit board
can be completely programmed in 10 to 25 sec-
onds. The four basic JTAG signals on Port C;
TMS, TCK, TDI, and TDO form the IEEE-1149.1
interface. The PSD Module does not implement
the IEEE-1149.1 Boundary Scan functions, but
uses the JTAG interface for ISP an 8032 debug.
The PSD Module can reside in a standard JTAG
chain with other JTAG devices and it will remain in
BYPASS mode when other devices perform JTAG
functions.
ISP programming time can be reduced as much as
30% by using two optional JTAG signals on Port
C, TSTAT and TERR, in addition to TMS, TCK,
TDI and TDO, and this is referred to as “6-pin
JTAG”. The FlashLINK JTAG programming cable
is available from STMicroelectronics and PSDsoft
Express software is available at no charge from
www.st.com/psm. More JTAG ISP information
maybe found in the section titled “JTAG ISP and
Debug” on page 137.
The MCU module is also included in the JTAG
chain within the uPSD33xx device for 8032 debug-
ging and emulation. While debugging, the PSD
Module is in BYPASS mode. Conversely, during
ISP, the MCU Module is in BYPASS mode.
Power Management. The PSD Module has bits
in csiop registers that are configured at run-time by
the 8032 to reduce power consumption of the
GPLD. The Turbo Bit in the PMMR0 Register can
be set to logic ’1’ and both PLDs will go to Non-
Turbo mode, meaning it will latch its outputs and
go to sleep until the next transition on its inputs.
There is a slight penalty in PLD performance
(longer propagation delay), but significant power
savings are realized. Going to Non-Turbo mode
may require an additional wait state in the 8032
SFR, BUSCON, because memory decode signals
are also delayed. The default state of the Turbo Bit
is logic '0,' meaning by default, the GPLD is in fast
Turbo mode until the Turbo mode is turned off.
Additionally, bits in csiop registers PMMR0 and
PMMR2 can be set by the 8032 to selectively
block signals from entering both PLDs which fur-
ther reduces power consumption. There is also an
Automatic Power Down counter that detects lack
of 8032 activity and reduces power consumption
on the PSD Module to its lowest level (see Power
Management, page 137).
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