UPSD33XX Datasheet, PDF (100/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
I²C Interface Control Register (S1CON)
Table 50. Serial Control Register S1CON (SFR DCh, Reset Value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CR2
ENI1
STA
STO
ADDR
AA
CR[1:0]
Details
Bit
Symbol
R/W
Function
This bit, along with bits CR1 and CR0, determine the SCL clock
7
CR2
R,W
frequency (f_SCL) when SIOE is in Master mode. These bits create a clock
divisor for f_OSC. See Table 51.
I²C Interface Enable
6
ENI1
R,W
0 = SIOE disabled, 1 = SIOE enabled. When disabled, both SDA and
SCL signals are in high impedance state.
START flag.
When set, Master mode is entered and SIOE generates a START
5
STA
R,W
condition only if the I²C bus is not busy. When a START condition is
detected on the bus, the STA flag is cleared by hardware. When the STA
bit is set during an interrupt service, the START condition will be
generated after the interrupt service.
STOP flag
4
STO
R,W
When STO is set in Master mode, the SIOE generates a STOP condition.
When a STOP condition is detected, the STO flag is cleared by
hardware. When the STO bit is set during an interrupt service, the STOP
condition will be generated after the interrupt service.
This bit is set when an address byte received in Slave mode matches the
3
ADDR
R,W
device address programmed into the S1ADR register. The ADDR bit
must be cleared with firmware.
Assert Acknowledge enable
If AA = 1, an acknowledge signal (low on SDA) is automatically returned
during the acknowledge bit-time on the SCL line when any of the
following three events occur:
1. SIOE in Slave mode receives an address that matches contents of
2
AA
R,W
S1ADR register
2. A data byte has been received while SIOE is in Master Receiver
mode
3. A data byte has been received while SIOE is a selected Slave
Receiver
When AA = 0, no acknowledge is returned (high on SDA during acknowl-
edge bit-time).
These bits, along with bit CR2, determine the SCL clock frequency (f_SCL)
1, 0
CR1, CR0
R,W
when SIOE is in Master mode. These bits create a clock divisor for f_OSC.
See Table 51 for values.
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