UPSD33XX Datasheet, PDF (118/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 60. SPICON1: SPI Interface Control Register 1 (SFR D7h, Reset Value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
–
TEIE
RORIE
TIE
Details
Bit
Symbol
R/W
Definition
7-4
–
–
Reserved
Transmission End Interrupt Enable
3
TEIE
RW
0 = Disable Interrupt for Transmission End
1 = Enable Interrupt for Transmission End
Receive Overrun Interrupt Enable
2
RORIE
RW
0 = Disable Interrupt for Receive Overrun
1 = Enable Interrupt for Receive Overrun
Transmission Interrupt Enable
1
TIE
RW
0 = Disable Interrupt for SPITDR empty
1 = Enable Interrupt for SPITDR empty
Reception Interrupt Enable
0
RIE
RW
0 = Disable Interrupt for SPIRDR full
1 = Enable Interrupt for SPIRDR full
Bit 0
RIE
Table 61. SPICLKD: SPI Prescaler (Clock Divider) Register (SFR D2h, Reset Value 04h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIV128
DIV64
DIV32
DIV16
DIV8
DIV4
–
–
Details
Bit
Symbol
R/W
Definition
7
DIV128
RW
0 = No division
1 = Divide f_OSC clock by 128
6
DIV64
RW
0 = No division
1 = Divide f_OSC clock by 64
5
DIV32
RW
0 = No division
1 = Divide f_OSC clock by 32
4
DIV16
RW
0 = No division
1 = Divide f_OSC clock by 16
3
DIV8
RW
0 = No division
1 = Divide f_OSC clock by 8
2
DIV4
RW
0 = No division
1 = Divide f_OSC clock by 4
1-0
Not Used
–
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