UPSD33XX Datasheet, PDF (24/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 5. SFR Memory Map with Direct Address and Reset Value
SFR
Addr
(hex)
SFR
Name
7
6
Bit Name and <Bit Address>
5
4
3
2
Reset Reg.
Value Descr.
1
0 _{(hex) with Link}
80
RESERVED
81
SP
SP[7:0]
Stack
07
Pointer
(SP), page
21
82
DPL
83
DPH
DPL[7:0]
DPH[7:0]
00
Data
Pointer
00 ^{(DPTR), p}
age 21
84
RESERVED
85 DPTC
–
AT
–
–
–
DPSEL[2:0]
Table
00 13., page
37
Table
86 DPTM
–
–
–
–
MD1[1:0]
MD0[1:0]
00 14., page
38
87 PCON SMOD0 SMOD1
–
Table
POR RCLK1 TCLK1 PD IDLE 00 24., page
50
88^{(1) TCON}
TF1
TR1
<8Fh> <8Eh>
TF0
<8Dh>
TR0
<8Ch>
IE1
<8Bh>
IT1
IE0 IT0
<8Ah> <89h> <88h>
00
Table
39., page
70
Table
89 TMOD GATE C/T
M1
M0 GATE C/T
M1 M0 00 40., page
72
8A
TL0
8B
TL1
8C
TH0
8D
TH1
TL0[7:0]
TL1[7:0]
TH0[7:0]
TH1[7:0]
00
Standard
00
Timer
00 ^{SFRs, pag}
e 69
00
8E P1SFS0
P1SFS0[7:0]
Table
00 29., page
60
8F P1SFS1
P1SFS1[7:0]
Table
00 30., page
60
90⁽¹⁾
P1
P1.7 P1.6
<97h> <96h>
P1.5
<95h>
P1.4
<94h>
P1.3
<93h>
P1.2
<92h>
P1.1 P1.0
<91h> <90h>
FF
Table
25., page
57
91 P3SFS
P3SFS[7:0]
Table
00 28., page
60
92 P4SFS0
P4SFS0[7:0]
Table
00 32., page
61
93 P4SFS1
P4SFS1[7:0]
Table
00 33., page
61
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