UPSD33XX Datasheet, PDF (145/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Figure 60. VM Register Example Corresponding to Memory Map Example of Figure 33
8032 Address
53 Other PLD Inputs
DPLD
RS0
CSBOOT0 - CSBOOT3
FS0 - FS7
Main Flash
Memory
CS
WR OE
CS
Secondary
Flash
Memory
WR OE
CS
SRAM
WR OE
VM Register = 0Ch
AI02869D
PSEN
WR
RD
Runtime Control Register Definitions (csiop)
The 39 csiop registers are defined in Table 79.
The 8032 can access each register by the address
offset (specified in Table 79) added to the csiop
base address that was specified in PSDsoft Ex-
press. Do not write to unused locations within the
csiop block of 256 registers, they should remain
logic zero.
Table 79. CSIOP Registers and their Offsets (in hexadecimal)
Register
Name
Port A
(80-pin)
Port B Port C Port D
Other
Description
Link
Data In
00h
01h 10h 11h
MCU I/O input mode. Read to obtain
current logic level of pins on Ports A, B,
C, or D. No WRITEs.
Table
95., page
172
Control
02h
03h
Selects MCUI/O or Latched Address
Out mode. Logic 0 = MCU I/O, 1 = 8032
Addr Out. Write to select mode. Read for
status.
Table
107., page
177
Data Out
04h
05h 12h 13h
MCU I/O output mode. Write to set logic
level on pins of Ports A, B, C, or D. Read
to check status. This register has no
effect if a port pin is driven by an OMC
output from PLD.
Table
99., page
172
Direction
06h
07h 14h 15h
MCU I/O mode. Configures port pin as
input or output. Write to set direction of
port pins.
Logic 1 = out, Logic 0 = in. Read to
check status.
Table
103., page
173
Drive Select
08h
09h 16h 17h
Write to configure port pins as either
CMOS push-pull or Open Drain on some Table
pins, while selecting high slew rate on 109., page
other pins. Read to check status. Default 179
output type is CMOS push-pull.
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