UPSD33XX Datasheet, PDF (190/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Forced Power Down (FDP). An alternative to
APD is FPD. The resulting power-savings is the
same, but the PDN signal in Figure 78., page 191
is set and Power-Down mode is entered immedi-
ately when firmware sets the FORCE_PD Bit to
logic '1' in the csiop Register PMMR3 (Bit 1). FPD
will override APD counter activity when
FORCE_PD is set. No external clock source for
the APD counter is needed. The FORCE_PD Bit is
cleared only by a reset condition.
Caution must be used when implementing FPD
because code memory goes off-line as soon as
PSD Module Power-Down mode is entered, leav-
ing the MCU with no instruction stream to execute.
The MCU Module must put itself into Power-Down
mode after it puts the PSD Module into Power-
Down Mode. How can it do this if code memory
goes off-line? The answer is the Pre-Fetch Queue
(PFQ) in the MCU Module. By using the instruction
scheme shown in the 8051 assembly code exam-
ple in Table 120, the PFQ will be loaded with the
final instructions to command the MCU Module to
Power Down mode after the PDS Module goes to
Power-Down mode. In this case, even though the
code memory goes off-line in the PSD Module, the
last few MCU instruction are sourced from the
PFQ.
Table 120. Forced Power-Down Example
PDOWN:
ANL
A8h, #7Fh
ORL
9Dh, #C0h
MOV
DPTR, #xxC7
CLR
JMP
NOP
A
LOOP
LOOP:
MOVX
@DPTR, A
MOV
MOV
JMP
87h, A
A, #02h
LOOP
; disable all interrupts
; ensure PFQ and BC are enabled
; load XDATA pointer to select PMMR3 register (xx = base
; address of csiop registers)
; clear A
; first loop - fill PFQ/BQ with Power Down instructions
; second loop - fetch code from PFQ/BC and set Power-
; Down bits for PSD Module and then MCU Module
; set FORCE_PD Bit in PMMR3 in PSD Module in second
; loop
; set PD Bit in PCON Register in MCU Module in second
; loop
; set power-down bit in the A Register, but not in PMMR3 or
; PCON yet in first loop
; uPSD enters into Power-Down mode in second loop
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