UPSD33XX Datasheet, PDF (89/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
More About UART Modes 2 and 3
For Mode 2, refer to the block diagram in Figure
32., page 90, and timing diagram in Figure
33., page 90. For Mode 3, refer to the block dia-
gram in Figure 34., page 91, and timing diagram in
Figure 35., page 91.
Keep in mind that the baud rate is programmable
to either 1/32 or 1/64 of f_OSC in Mode 2, but Mode
3 uses a variable baud rate generated from Timer
1 or Timer 2 rollovers.
The receive portion is exactly the same as in Mode
1. The transmit portion differs from Mode 1 only in
the 9th bit of the transmit shift register.
Transmission is initiated by any instruction which
writes to SBUF. At the end of a write operation to
SBUF, the TB8 Bit is loaded into the 9th position of
the transmit shift register and flags the TX Control
unit that a transmission is requested. Transmis-
sion actually starts at the end of the MCU the ma-
chine cycle following the next rollover in the divide-
by-16 counter. Thus, the bit times are synchro-
nized to the divide-by-16 counter, not to the writing
of SBUF. Transmission begins with activation of
SEND which puts the start bit at pin TxD. One bit
time later, DATA is activated, which enables the
output bit of the transmit shift register to pin TxD.
The first shift pulse occurs one bit time after that.
The first shift clocks a '1' (the stop bit) into the 9th
bit position of the shift register. There-after, only
zeros are clocked in. Thus, as data bits shift out to
the right, zeros are clocked in from the left. When
bit TB8 is at the output position of the shift register,
then the stop bit is just to the left of TB8, and all po-
sitions to the left of that contain zeros. This condi-
tion flags the TX Control unit to do one last shift
and then deactivate SEND, and set the interrupt
flag, TI. This occurs at the 11th divide-by 16 roll-
over after writing to SBUF.
Reception is initiated by a detected 1-to-0 transi-
tion at pin RxD. For this purpose RxD is sampled
at a rate of 16 times whatever baud rate has been
established. When a transition is detected, the di-
vide-by-16 counter is immediately reset, and 1FFH
is written to the input shift register. At the 7th, 8th,
and 9th counter states of each bit time, the bit de-
tector samples the value of RxD. The value ac-
cepted is the value that was seen in at least 2 of
the 3 samples. If the value accepted during the
first bit time is not '0,' the receive circuits are reset
and the unit goes back to looking for another '1'-to-
'0' transition. If the start bit proves valid, it is shifted
into the input shift register, and reception of the
rest of the frame will proceed. As data bits come in
from the right, '1s' shift out to the left. When the
start bit arrives at the left-most position in the shift
register (which in Modes 2 and 3 is a 9-bit regis-
ter), it flags the RX Control unit to do one last shift,
load SBUF and RB8, and set the interrupt flag RI.
The signal to load SBUF and RB8, and to set RI,
will be generated if, and only if, the following con-
ditions are met at the time the final shift pulse is
generated:
1. RI = 0, and
2. Either SM2 = 0, or the received 9th data bit = 1.
If either of these conditions is not met, the received
frame is irretrievably lost, and RI is not set. If both
conditions are met, the received 9th data bit goes
into RB8, and the first 8 data bits go into SBUF.
One bit time later, whether the above conditions
were met or not, the unit goes back to looking for
a '1'-to-'0' transition on pin RxD.
89/231