UPSD33XX Datasheet, PDF (213/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

Figure 90. Input to Output Disable / Enable
uPSD33xx
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 137. CPLD Combinatorial Timing (5V PSD Module)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo ^Slew
Off _rate⁽¹⁾
Unit
t_PD(2)
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
20
+ 2 + 10 – 2 ns
t_EA
CPLD Input to CPLD Output
Enable
21
+ 10 – 2 ns
t_ER
CPLD Input to CPLD Output
Disable
21
+ 10 – 2 ns
t_ARP
CPLD Register Clear or Preset
Delay
21
+ 10 – 2 ns
t_ARPW
CPLD Register Clear or Preset
Pulse Width
10
+ 10
ns
t_ARD CPLD Array Delay
Any
macrocell
11
+2
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t_PD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
Table 138. CPLD Combinatorial Timing (3V PSD Module)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo Slew
Off _rate⁽¹⁾
Unit
t_PD(2)
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
35
+ 4 + 20 – 6 ns
t_EA
CPLD Input to CPLD Output
Enable
38
+ 20 – 6 ns
t_ER
CPLD Input to CPLD Output
Disable
38
+ 20 – 6 ns
t_ARP
CPLD Register Clear or
Preset Delay
35
+ 20 – 6 ns
t_ARPW
CPLD Register Clear or
Preset Pulse Width
18
+ 20
ns
t_ARD CPLD Array Delay
Any
macrocell
20
+4
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
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