UPSD33XX Datasheet, PDF (54/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
GPIO Input. To use a GPIO port pin as an input,
the low-side driver to ground must be disabled, or
else the true logic level being driven on the pin by
an external device will be masked (always reads
logic '0'). So to make a port pin “input ready”, the
corresponding bit in the SFR must have been set
to a logic '1' prior to reading that SFR bit as an in-
put. A reset condition forces SFRs P1, P3, and P4
to FFh, thus all three ports are input ready after re-
set.
When a pin is used as an input, the stronger pull-
up “A” maintains a solid logic '1' until an external
device drives the input pin low. At this time, pull-up
“A” is automatically disabled, and only pull-up “B”
will source the external device I_IH uA, consistent
with standard 8051 architecture.
GPIO Bi-Directional. It is possible to operate indi-
vidual port pins in bi-directional mode. For an out-
put, firmware would simply write the
corresponding SFR bit to logic '1' or '0' as needed.
But before using the pin as an input, firmware must
first ensure that a logic '1' was the last value writ-
ten to the corresponding SFR bit prior to reading
that SFR bit as an input.
GPIO Current Capability. A GPIO pin on Port 4
can sink twice as much current than a pin on either
Port 1 or Port 3 when the low-side driver is output-
ting a logic '0' (I_OL). See the DC specifications at
the end of this document for full details.
Reading Port Pin vs. Reading Port Latch. When
firmware reads the GPIO ports, sometimes the ac-
tual port pin is sampled in hardware, and some-
times the port SFR latch is read and not the actual
pin, depending on the type of MCU instruction
used. These two data paths are shown in Figure
17., page 56 through Figure 19., page 57. SFR
latches are read (and not the pins) only when the
read is part of a read-modify-write instruction and
the write destination is a bit or bits in a port SFR.
These instructions are: ANL, ORL, XRL, JBC,
CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All
other types of reads to port SFRs will read the ac-
tual pin logic level and not the port latch. This is
consistent with 8051 architecture.
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