UPSD33XX Datasheet, PDF (131/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 72. PCA Status Register PCASTA (SFR 0A5h, Reset Value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
OVF1
INTF5
INTF4
INTF3
OVF0
INTF2
Details
Bit
Symbol
Function
PCA1 Counter OverFlow flag
Bit 1
INTF1
Bit 0
INTF0
7
OFV1 Set by hardware when the counter rolls over. OVF1 flags an interrupt if Bit EOVFI in
PCACON1 is set. OVF1 may be set with either hardware or software but can only be
cleared with software.
TCM5 Interrupt flag
6
INTF5
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM4 Interrupt flag
5
INTF4
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM3 Interrupt flag
4
INTF3
Set by hardware when a match or capture event occurs.
Must be clear with software.
PCA0 Counter OverFlow flag
3
OVF0 Set by hardware when the counter rolls over. OVF0 flags an interrupt if Bit EOVFI in
PCACON0 is set. OVF1 may be set with either hardware or software but can only be
cleared with software.
TCM2 Interrupt flag
2
INTF2
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM1 Interrupt flag
1
INTF1
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM0 Interrupt flag
0
INTF0
Set by hardware when a match or capture event occurs.
Must be clear with software.
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