UPSD33XX Datasheet, PDF (179/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
JTAG ISP Mode. Four of the pins on Port C are
based on the IEEE 1149.1 JTAG specification and
are used for In-System Programming (ISP) of the
PSD Module and debugging of the 8032 MCU
Module. These pins (TDI, TDO, TMS, TCK) are
dedicated to JTAG and cannot be used for any
other I/O function. There are two optional pins on
Port C (TSTAT and TERR) that can be used to re-
duce programming time during ISP. See JTAG
ISP and JTAG Debug, page 195.
Other Port Capabilities. It is possible to change
the type of output drive on the ports at run-time. It
is also possible to read the state of the output en-
able signal of the output driver at run-time. The fol-
lowing sections provide the details.
Port Pin Drive Options. The csiop Drive Select
registers allow reconfiguration of the output drive
type for certain pins on Ports A, B, C, and D. The
8032 can change the default drive type setting at
run-time. The is no action needed in PSDsoft Ex-
press to change or define these pin output drive
types. Figure 69., page 169 shows the csiop Drive
Select register output controlling the pin output
driver. The default setting for drive type for all pins
on Ports A, B, C, and D is a standard CMOS push-
pull output driver.
Note: When a pin on Port A, B, C, D is not used as
an output and has no external device driving it as
an input (floating pin), excess power consumption
can be avoided by placing a weak pull-up resistor
(100KΩ) to V_DD which keeps the CMOS input pin
from floating.
Drive Select Registers. The csiop Drive Select
Registers will configure a pin output driver as
Open Drain or CMOS push/pull for some port pins,
and controls the slew rate for other port pins. An
external pull-up resistor should be used for pins
configured as Open Drain, and the resistor should
be sized not to exceed the current sink capability
of the pin (see DC specifications). Open Drain out-
puts are diode clamped, thus the maximum volt-
age on an pin configured as Open Drain is V_DD +
0.7V.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to
logic '1.'
Note: The slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to '1.' The default rate is standard slew
rate (see AC specifications).
Table 109 through Table 112., page 180 show the
csiop Drive Registers for Ports A, B, C, and D. The
tables summarize which pins can be configured as
Open Drain outputs and which pins the slew rate
can be changed. The default output type is CMOS
push/pull output with normal slew rate.
Enable Out Registers. The state of the output
enable signal for the output driver at each pin on
Ports A, B, C, and D can be read at any time by the
8032 when it reads the csiop Enable Output regis-
ters. Logic '1' means the driver is in output mode,
logic ’0’ means the output driver is in high-imped-
ance mode, making the pin suitable for input mode
(read by the input buffer shown in Figure
69., page 169). Figure 69 shows the three sources
that can control the pin output enable signal: a
product term from AND-OR array; the csiop Direc-
tion register; or the Peripheral I/O Mode logic (Port
A only). The csiop Enable Out registers represent
the state of the final output enable signal for each
port pin driver, and are defined in Table
113., page 180 through Table 116., page 180.
Table 109. Port A Pin Drive Select Register⁽¹⁾ (address = csiop + offset 08h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PA7
PA6
PA5
PA4
PA3
Open Drain Open Drain Open Drain Open Drain Slew Rate
PA2
Slew Rate
PA1
Slew Rate
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
3. Default state for register is 00h after reset or power-up
Bit 0
PA0
Slew Rate
Table 110. Port B Pin Drive Select Register (address = csiop + offset 09h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PB7
PB6
PB5
PB4
PB3
Open Drain Open Drain Open Drain Open Drain Slew Rate
PB2
Slew Rate
PB1
Slew Rate
Note: 1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
2. Default state for register is 00h after reset or power-up
Bit 0
PB0
Slew Rate
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