UPSD33XX Datasheet, PDF (122/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 64. ADCPS Register Details (SFR 94h, Reset Value 00h)
Bit
Symbol
Function
7:4
–
Reserved
ADC Conversion Reference Clock Enable
3
ADCCE _{0 = ADC reference clock is disabled (default)}
1 = ADC reference clock is enabled
ADC Reference Clock PreScaler
Only three Prescaler values are allowed:
2:0
ADCPS[2:0] _{ADCPS[2:0] = 0, for fOSC frequency 16MHz or less. Resulting ADC clock is fOSC.}
ADCPS[2:0] = 1, for f_OSC frequency 32MHz or less. Resulting ADC clock is f_OSC/2.
ADCPS[2:0] = 2, for f_OSC frequency 32MHz > 40MHz. Resulting ADC clock is f_OSC/4.
Table 65. ADAT0 Register (SFR 95H, Reset Value 00h)
Bit
Symbol
7:0
–
Store ADC output, Bit 7 - 0
Function
Table 66. ADAT1 Register (SFR 96h, Reset Value 00h)
Bit
Symbol
7:2
–
Reserved
1.. 0
–
Store ADC output, Bit 9, 8
Function
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