UPSD33XX Datasheet, PDF (47/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 21. CCON0: Clock Control Register (SFR F9h, reset value 10h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
DBGCE
CPUAR
CPUPS[2:0]
Details
Bit
Symbol
R/W
Definition
7
–
–
Reserved
6
–
–
Reserved
5
–
–
Reserved
Debug Unit Breakpoint Comparator Enable
Bit 0
4
DBGCE
R,W
0 = JTAG Debug Unit comparators are disabled
1 = JTAG Debug Unit comparators are enabled (Default condition after
reset)
Automatic MCU Clock Recovery
3
CPUAR
R,W
0 = There is no change of CPUPS[2:0] when an interrupt occurs.
1 = Contents of CPUPS[2:0] automatically become 000b whenever any
interrupt occurs.
MCUCLK Pre-Scaler
000b: f_MCU = f_OSC (Default after reset)
001b: f_MCU = f_OSC/2
2:0
CPUPS
R,W
010b: f_MCU = f_OSC/4
011b: f_MCU = f_OSC/8
100b: f_MCU = f_OSC/16
101b: f_MCU = f_OSC/32
110b: f_MCU = f_OSC/1024
111b: f_MCU = f_OSC/2048
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