UPSD33XX Datasheet, PDF (211/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Figure 89. External WRITE Cycle (80-pin Device Only)
ALE
PSEN
WR
MCU
AD0 - AD7
MCU
A8 - A11
tLHLL
tLLWL
tAVLL
tLLAX
A0-A7
tAVWL
tWHLH
tWLWH
tWHQX
tQVWH
DATA OUT
A0-A7
INSTR IN
A8-A11
A8-A11
AI07877
Table 134. External WRITE Cycle AC Characteristics (3V or 5V Device)
Symbol
Parameter
40MHz Oscillator⁽¹⁾
Min
Max
Variable Oscillator
1/t_CLCL = 8 to 40MHz
Min
Max
t_LHLL ALE pulse width
17
t_CLCL – 8
t_AVLL Address Setup to ALE
13
t_CLCL – 12
t_LLAX Address hold after ALE
7.5
0.5t_CLCL – 5
t_{WLWH WR pulse width}⁽²⁾
40
xt_CLCL – 10
t_LLWL ALE to WR
7.5
0.5t_CLCL – 5
t_AVWL Address valid to WR
27.5
1.5t_CLCL – 10
t_WHLH WR High to ALE High
6.5
14.5
0.5t_CLCL – 6 0.5t_CLCL + 2
t_{QVWH Data setup before WR}^(y)
20
yt_CLCL – 5
t_WHQX Data hold after WR
6.5
14.5
0.5t_CLCL – 6 0.5t_CLCL + 2
Note: 1. BUSCON Register is configured for 4 PFQCLK.
2. Refer to Table 135, page 151 for “n” and “m” values.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 135. External Clock Drive
Symbol
Parameter⁽¹⁾
t_CLCL
t_CHCX
t_CLCX
t_CLCH
t_CHCL
Oscillator period
High time
Low time
Rise time
Fall time
40MHz Oscillator
Min
Max
Variable Oscillator
1/t_CLCL = 8 to 40MHz
Unit
Min
Max
25
125
ns
10
t_CLCL – t_CLCX ns
10
t_CLCL – t_CLCX ns
10
ns
10
ns
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