UPSD33XX Datasheet, PDF (138/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Security and NVM Sector Protection. A pro-
grammable security bit in the PSD Module pro-
tects its contents from unauthorized viewing and
copying. The security bit is specified in PSDsoft
Express and programmed into the uPSD33xx with
JTAG. Once set, the security bit will block access
of JTAG programming equipment to the PSD Mod-
ule Flash memory and PLD configuration, and also
blocks JTAG debugging access to the MCU Mod-
ule. The only way to defeat the security bit is to
erase the entire PSD Module using JTAG (the
erase command is the only JTAG command al-
lowed after the security bit has been set), after
which the device is blank and may be used again.
Additionally and independently, the contents of
each individual Flash memory sector can be write
protected (sector protection) by configuration with
PSDsoft Express. This is typically used to protect
8032 boot code from being corrupted by inadvert-
ent WRITEs to Flash memory from the 8032.
Status of sector protection bits may be read (but
not written) using two registers in csiop space.
Memory Mapping
There many different ways to place (or map) the
address range of PSD Module memory and I/O
depending on system requirements. The DPLD
provides complete mapping flexibility. Figure 53
shows one possible system memory map. In this
example, 128K bytes of Main Flash memory for a
uPSD3333 device is in 8032 program address
space, and 32K bytes of Secondary Flash memo-
ry, the SRAM, and csiop registers are all in 8032
XDATA space.
In Figure 53, the nomenclature fs0..fs7 are desig-
nators for the individual sectors of Main Flash
memory, 16K bytes each. CSBOOT0..CSBOOT3
are designators for the individual Secondary Flash
memory segments, 8K bytes each. rs0 is the des-
ignator for SRAM, and csiop designates the PSD
Module control register set.
The designer may easily specify memory mapping
in a point-and-click software environment using
PSDsoft Express, creating a non-volatile configu-
ration when the DPLD is programmed using
JTAG.
8032 Program Address Space. In the example
of Figure 53, six sectors of Main Flash memory
(fs2.. fs7) are paged across three memory pages
in the upper half of program address space, and
the remaining two sectors of Main Flash memory
(fs0, fs1) reside in the lower half of program ad-
dress space, and these two sectors are indepen-
dent of paging (they reside in “common” program
address space). This paged memory example is
quite common and supported by many 8051 soft-
ware compilers.
8032 Data Address Space (XDATA). Four sec-
tors of Secondary Flash memory reside in the up-
per half of 8032 XDATA space in the example of
Figure 53. SRAM and csiop registers are in the
lower half of XDATA space. The 8032 SFR regis-
ters and local SRAM inside the 8032 MCU Module
do not reside in XDATA space, so it is OK to place
PSD Module SRAM or csiop registers at an ad-
dress that overlaps the address of internal 8032
MCU Module SRAM and registers.
Figure 53. Typical System Memory Map
8032 PROGRAM SPACE
(PSEN)
Page 0 Page 1 Page 2
FFFFh
fs3
16KB
C000h
8000h
fs2
16KB
fs5
16KB
fs7
16KB
fs4
16KB
fs6
16KB
8032 XDATA
SPACE
(RD and WR)
Page X
csboot3
8KB
FFFFh
E000h
csboot2
8KB _C000h
csboot1
8KB
csboot0
8KB
A000h
8000h
fs1, 16KB
Common Memory to All Pages
4000h
fs0, 16KB
Common Memory to All Pages
0000h
System
I/O
csiop
256B
2000h
rs0, 8KB
0000h
AI09173
138/231