UPSD33XX Datasheet, PDF (83/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 46. SCON1: Serial Port UART1 Control Register (SFR D8h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Details
Bit
Symbol
R/W
Definition
7
SM0
R,W
Serial Mode Select, See Table 44., page 81. Important, notice bit order
of SM0 and SM1.
[SM0:SM1] = 00b, Mode 0
6
SM1
R,W
[SM0:SM1] = 01b, Mode 1
[SM0:SM1] = 10b, Mode 2
[SM0:SM1] = 11b, Mode 3
Serial Multiprocessor Communication Enable.
Mode 0: SM2 has no effect but should remain 0.
5
SM2
R,W
Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI active if stop
bit = 1.
Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th bit is
ignored. If SM2=1, RI active when 9th bit = 1.
Receive Enable.
4
REN
R,W
If REN=0, UART reception disabled. If REN=1, reception is enabled
3
TB8
R,W
TB8 is assigned to the 9th transmission bit in Mode 2 and 3. Not used in
Mode 0 and 1.
Mode 0: RB8 is not used.
2
RB8
R,W
Mode 1: If SM2 = 0, the RB8 is the level of the received stop bit.
Mode 2 and 3: RB8 is the 9th data bit that was received in Mode 2 and
3.
Transmit Interrupt flag.
1
TI
R,W
Causes interrupt at end of 8th bit time when transmitting in Mode 0, or at
beginning of stop bit transmission in other modes. Must clear flag with
firmware.
Receive Interrupt flag.
0
RI
R,W
Causes interrupt at end of 8th bit time when receiving in Mode 0, or
halfway through stop bit reception in other modes (see SM2 for
exception). Must clear this flag with firmware.
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