UPSD33XX Datasheet, PDF (184/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Figure 76. Port C Structure
FROM AND-
OR ARRAY
FROM PLD
INPUT BUS
PT OUTPUT ENABLE, .OE (JTAG STATE MACHINE
AUTOMATICALLY CONTROLS OE FOR JTAG SIGNALS)
PSD MODULE RESET
Q ^DIRECTION
CSIOP
REGIS-
8032 ^TERS
DATA
Q
DRIVE
BITS _D
DRIVE TYPE SELECT⁽²⁾
I/O PORT C
LOGIC
V_DD/V_BAT(1)
PULL-UP
ONLY ON
50k _{JTAG TDI,}
TMS, TCK
SIGNALS
8032
WR
(MCUI/O)
DATA OUT
Q
CLR _RESET
8032
DATA
BIT
1 ^DIRECTION
P ₂ ^{DRIVE SELECT}
D _{DATA OUT}
B _{3 (MCUI/O)}
M 4 ^{ENABLE OUT}
U
X ₅ DATA IN (MCUI/O)
PSDsoft
1^O
U
T
P
U
2T
3
4
M
U
5_X
OUTPUT
ENABLE
PIN
OUTPUT
V_DD
V_DD/V_BAT(1)
TYPICAL
PIN,
PORT C
PIN
CMOS _INPUT
BUFFER
8032 RD
ONE of 6
CSIOP
REGISTERS
FROM OMC
ALLOCATOR
FROM OMC OUTPUT (MCELLBCx)
FROM SRAM
BACK-UP CIRCUIT
FROM FLASH MEMORIES
TO/FROM JTAG
STATE MACHINE
STANDBY ON⁽²⁾
RDY/BSY⁽²⁾
TDO, TSTAT⁽²⁾, TERR⁽²⁾
TDI, TMS, TCK
NO
HYSTERESIS
TO IMCs
IMCC2, IMCC3,
IMCC4, IMCC7
TO SRAM
BATTERY
BACK-UP
CIRCUIT⁽²⁾
AI09181
Note: 1. Pull-up switches to V_BAT when SRAM goes to battery back-up mode.
2. Optional function on a specific Port C pin.
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